Re: [Gems-users] Help with Opal Tester


Date: Fri, 8 Jul 2005 08:45:54 -0500 (CDT)
From: Luke Yen <lyen@xxxxxxxxxxx>
Subject: Re: [Gems-users] Help with Opal Tester
Ankit,

  After a quick glance at the tester code, it seems like the tester
requires all trace files (instruction map, TLB, memory, processor state)
to be present in order to execute correctly.  In your trace directory
you should have 4 files, all non-empty.  Here is an example, using the
trace name "test-trace" :

  test-trace
  imap-test-trace.map
  mem-test-trace
  tlb-test-trace

  I believe you can generate all 4 files using the built-in Opal tracing
utility.  However having never used this I recommend looking at the trace
code for instructions on how to do so.

  By the way, the "mop" instructions are Opal's internal instruction
opcode indicating a TLB miss has occurred.  This special instruction flows
through the pipeline and when any instruction is squashed in the retire
stage it starts handling the TLB miss.

  Luke

On Thu, 7 Jul 2005, Ankit Jalote wrote:

> Hi,
> I am having some difficulty running Opal tester. When I run the tester
> on the trace file created using opal trace features -
> 1- First of all it is not able to find tlb-<trace_file>.
> 2- To skip the first problem I just created an empty tlb trace file.
> 3- But after that tester gives lot of warnings and error messages before
> starting to run the smulation (output attached below)
> 4- And finally only opcode it seems to execute in mop. The statistics
> show that there were no  memory or branch instruction either.
>
> Can you please help me with this.
>
> Thanks,
> Ankit
>
>
>
> Following is the output of the command -  x86-linux/bin/tester.exec
> ./config/std-64-L1:64K:2-L2:4M:4.txt  <dir> trace-filename 10000
> ************************************************************************************************
>
>
> sim-simics-api: V 0.5: initializing simics API simulator
> simdist12: warning: unimplemented simics API system/simdist12.C:367
> simdist12: warning: unimplemented simics API system/simdist12.C:373
> simdist12: warning: unimplemented simics API system/simdist12.C:373
> simdist12: warning: unimplemented simics API system/simdist12.C:373
> simdist12: warning: unimplemented simics API system/simdist12.C:373
> simdist12: warning: unimplemented simics API system/simdist12.C:426
> simdist12: warning: unimplemented simics API system/simdist12.C:359
> error: unable to register queue interface
> hfa_init_local done:
> read configuration: ./config/std-64-L1:64K:2-L2:4M:4.txt
> error: "PSEQ_SLIDING_WINSIZE" not found. unable to set value.
> simdist12: warning: unimplemented simics API system/simdist12.C:275
> Ln constructor: block size: 64B, 4x assoc, 16384 sets.  4194304B total
> Ln constructor: block size: 64B, 2x assoc, 512 sets.  65536B total
> Ln constructor: block size: 64B, 2x assoc, 512 sets.  65536B total
> Reading TLB translation information...
> tracefile_t: successfully opened for reading
> Initial primary context: 0x28e
> simulate: completed 10001 instructions, cycle: 70007
> *** Opcode stats:
> ###: decode              seen        success function     fail
> Unmatched     0
> 428: mop               10,001              0        0   10,001
> TOTALI    :         10,001              0        0   10,001
> NON_COMP  :              0
> Percent functional: 0.000000
> Percent correct      : 0.000000
>
> *** Latency and Squashes
>
> 000: opcode    # squashed # non-comp mem latency  min max avg exec
> 428: mop           20,002          0      0    0.0    1   1    1.0
> SQUASHED  :         20,002
>
> *** Trap   stats:
>  [Trap#]  Times-Taken  Simics-Taken    Name
>  [100]          10001               0  Fast_Instruction_Access_MMU_Miss
> *** Internal exception stats:
> ###: seen    name
> *** ASI    stats:
>  ASI     Reads   Writes  Atomics
> *** Branch   stats: (user, kernel, total)
>  Type           Preds      Retired        Right       Wrong    %Right
>   NONE              0            0            0            0  U:  0.00%
>   NONE              0            0            0            0  K:  0.00%
>   NONE              0            0            0            0  T:  0.00%
>   UNCOND            0            0            0            0  U:  0.00%
>   UNCOND            0            0            0            0  K:  0.00%
>   UNCOND            0            0            0            0  T:  0.00%
>   COND              0            0            0            0  U:  0.00%
>   COND              0            0            0            0  K:  0.00%
>   COND              0            0            0            0  T:  0.00%
>   PCOND             0            0            0            0  U:  0.00%
>   PCOND             0            0            0            0  K:  0.00%
>   PCOND             0            0            0            0  T:  0.00%
>   CALL              0            0            0            0  U:  0.00%
>   CALL              0            0            0            0  K:  0.00%
>   CALL              0            0            0            0  T:  0.00%
>   RETURN            0            0            0            0  U:  0.00%
>   RETURN            0            0            0            0  K:  0.00%
>   RETURN            0            0            0            0  T:  0.00%
>   INDIRE            0            0            0            0  U:  0.00%
>   INDIRE            0            0            0            0  K:  0.00%
>   INDIRE            0            0            0            0  T:  0.00%
>   CWP               0            0            0            0  U:  0.00%
>   CWP               0            0            0            0  K:  0.00%
>   CWP               0            0            0            0  T:  0.00%
>   TRAP_R            0            0            0            0  U:  0.00%
>   TRAP_R            0            0            0            0  K:  0.00%
>   TRAP_R            0            0            0            0  T:  0.00%
>   TRAP              0            0            0            0  U:  0.00%
>   TRAP              0            0            0            0  K:  0.00%
>   TRAP              0            0            0            0  T:  0.00%
>   PRIV              0            0            0            0  U:  0.00%
>   PRIV              0            0            0            0  K:  0.00%
>   PRIV              0            0            0            0  T:  0.00%
>   TOTALB            0            0            0            0    0.00%
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