Re: [Gems-users] L1 bypassing?

[Mike Marty <mikem@xxxxxxxxxxx>]

Chris,

I suspect that the protocol you used doesn't have L1 cache statistics
hooked up correctly.  Which protocol was this?

--Mike


> Hi,
>
> after a simulation of a uniprocessor machine with warm caches, I got the
> following results:
>
>
>
> ----------------------------
> L1D_cache cache stats:
>   L1D_cache_total_misses: 0
>   L1D_cache_total_demand_misses: 0
>   L1D_cache_total_prefetches: 0
>   L1D_cache_total_sw_prefetches: 0
>   L1D_cache_total_hw_prefetches: 0
>   L1D_cache_misses_per_transaction: 0
>   L1D_cache_misses_per_instruction: 0
>   L1D_cache_instructions_per_misses: NaN
>
>   L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN
> |standard
> deviation: NaN | 0 ]
>
> L1I_cache cache stats:
>   L1I_cache_total_misses: 0
>   L1I_cache_total_demand_misses: 0
>   L1I_cache_total_prefetches: 0
>   L1I_cache_total_sw_prefetches: 0
>   L1I_cache_total_hw_prefetches: 0
>   L1I_cache_misses_per_transaction: 0
>   L1I_cache_misses_per_instruction: 0
>   L1I_cache_instructions_per_misses: NaN
>
>   L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN
> |standard
> deviation: NaN | 0 ]
>
> L2_cache cache stats:
>   L2_cache_total_misses: 74762
>   L2_cache_total_demand_misses: 42876
>   L2_cache_total_prefetches: 31886
>   L2_cache_total_sw_prefetches: 31886
>   L2_cache_total_hw_prefetches: 0
>   L2_cache_misses_per_transaction: 74762
>   L2_cache_misses_per_instruction: 7.4762e-05
>   L2_cache_instructions_per_misses: 13375.8
> ----------------------------
>
>
>
> What confuses me is that there are L2 misses, but no L1 misses, which
> seems to be a contradiction if inclusive caches are used. How can the
> result be explained? And from where can I get the total number of
> accesses to the individual levels to compute the miss rate?
>
> Cheers,
> Chris
>
>
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