[Gems-users] logtm/tourmaline with ultrasparc II

[郭锐 <timmyguo@xxxxxxxxxxxxxxxx>]

Hi all,
I'm trying to bring LogTM/tourmaline to work for me. Here is my story.

I don't have a sun license to use the Sarek target machine in Simics. So I
have to use the Bagle target machine instead (A Suse7.3 Linux dump is
available at Simics site). The most significant difference between the two
may be the processor type. The former uses UltraSPARC-III+ while the latter
uses UltraSPARC-II. And these two processors have different number of
control registers, so the LogTM and Tourmaline (the Generic controller)
doesn't work for Bagle out of box.

Here's the original code in "RegisterStateWindowed.C" that hardcoded the
control register numbers:
  for(i=0; i < 126 ; i++){
    if((i <= 31) ||
       (i == 39 || (i == 43)) ||  // tick/stick
       (i == 45) ||               // pstate
       (i >= 53 && i <= 57) ||    // invalid
       (i >= 63 && i <= 67) ||    // invalid
       (i >= 73 && i <= 77) ||    // invalid
       (i >= 83 && i <= 87) ||    // invalid
       //(i >= 91 && i <= 95) ||    // window state
       (i >= 100 && i <= 110) || // interrupt status (just added)
       (i >= 111 && i <= 119))   // interrupt address
      {
        continue;
      }
    m_controlRegisterNumbers.insertAtBottom(i);
  }

After comparing the register numbering for the two processors in Simics, I
modified it to this:
  for(i=0; i < 111 ; i++){
    if((i <= 31) ||
       (i == 39) ||               // tick
       (i == 43) ||               // pstate
       (i >= 51 && i <= 55) ||    // invalid
       (i >= 61 && i <= 65) ||    // invalid
       (i >= 71 && i <= 75) ||    // invalid
       (i >= 81 && i <= 85) ||    // invalid
       (i >= 97 && i <= 102) || // interrupt status (just added)
       (i >= 103 && i <= 106))   // interrupt address
      {
        continue;
      }
    m_controlRegisterNumbers.insertAtBottom(i);
  }

I'm not quite sure of this modification, because I'm a stranger to SPARC. It
does work sometimes, but it can cause [[kernel panic]] or deadlock in my
benchmark too. Can anybody check it for me?

Here are the tables of control register numbering for the two processors in
Simics:

UltraSPARC II
pc			32
npc			33
y			34
ccr			35
fprs			36
fsr			37
asi			38
tick			39
gsr			40
tick_cmpr		41
dcr			42
pstate			43
tl			44
pil			45
tpc1			46
tpc2			47
tpc3			48
tpc4			49
tpc5			50
tnpc1			56
tnpc2			57
tnpc3			58
tnpc4			59
tnpc5			60
tstate1			66
tstate2			67
tstate3			68
tstate4			69
tstate5			70
tt1			76
tt1			76
tt2			77
tt3			78
tt4			79
tt5			80
tba			86
ver			87
cwp			88
cansave			89
canrestore		90
otherwin		91
wstate			92
cleanwin		93
softint			94
upa_config		95
ecache_error_enable		96
asynchronous_fault_status	97
asynchronous_fault_address	98
out_intr_data0			99
out_intr_data1			100
out_intr_data2			101
intr_dispatch_status		102
in_intr_data0			103
in_intr_data1			104
in_intr_data2			105
intr_receive			106
serial_id			107
pic			108
pcr			109
mid			110

and UltraSPARC III+
pc			32
npc			33
y			34
ccr			35
fprs			36
fsr			37
asi			38
tick			39
gsr			40
tick_cmpr		41
dcr			42
stick			43
stick_cmpr		44
pstate			45
tl			46
pil			47
tpc1			48
tpc2			49
tpc3			50
tpc4			51
tpc5			52
tnpc1			58
tnpc2			59
tnpc3			60
tnpc4			61
tnpc5			62
tstate1			68
tstate2			69
tstate3			70
tstate4			71
tstate5			72
tt1			78
tt2			79
tt3			80
tt4			81
tt5			82
tba			88
ver			89
cwp			90
cansave			91
canrestore		92
otherwin		93
wstate			94
cleanwin		95
softint			96
safari_config			97
safari_address			98
ecache_error_enable		99
asynchronous_fault_status	100
asynchronous_fault_address	101
out_intr_data0			102
out_intr_data1			103
out_intr_data2			104
out_intr_data3			105
out_intr_data4			106
out_intr_data5			107
out_intr_data6			108
out_intr_data7			109
intr_dispatch_status		110
in_intr_data0			111
in_intr_data1			112
in_intr_data2			113
in_intr_data3			114
in_intr_data4			115
in_intr_data5			116
in_intr_data6			117
in_intr_data7			118
intr_receive			119
serial_id			120
pic			121
pcr			122
mid			123

Thanks very much!

PS: I wonder why the original code could work, it tries to read the
registers 124 and 125, which doesn't exists even in UltraSPARC III+.

G.R.