Re: [Gems-users] cache statistics

[Dan Gibson <degibson@xxxxxxxx>]

Mladen,

Some of the protocols do not do a great job in profiling the L1s. We 
often focus on off-chip misses, which is why several protocols do not 
profile L1s at all.
In ruby, there is a single instance of SimicsDriver, but one instance of 
SimicsProcessor for each processor -- so all of a given processor's 
accesses pass through its SimicsProcessor.
There is also one Sequencer for each processor -- since SimicsProcessor 
is really part of the interface, Sequencer is probably where you should 
add any L1 profiling code.
Regards,
Dan

Mladen Nikitovic wrote:
> Hi,
>
> I need some clarification to understand the statistics generated by
> ruby_dump_stats. I'm especially interested in cache-specific statistics. If
> I understand it correctly, there's a profiler that collects data about
> number of misses in the cache. However, the total number of cache requests
> is not visible here. There are entries, "Data requests" and "Insn requests",
> that are available under "Simics Driver Transaction Stats". 
>
> Should I interpret these two entries as the total number of L1D and L1I
> requests respectively?
>
> My impression was that there is one L1 cache per processor, but when looking
> at the ruby code or statistics I see no evidence of that. Was my expectation
> wrong? I'm using the MOSI_SMP_bcast protocol.
>
> Under "Chip Stats" there are "event counts" for L1 cache. But, if I sum up
> the number of Load, Ifetch, and Store, I do not get the same number as the
> "Data requests" and "Insn requests" from "Simics Driver Transaction Stats."
>
> Would also like to get number of L2 accesses, but that should correspond to
> L1I and L1D misses specified in the Profiler stats section, right?
>
> My goal is to collect statistics for each L1 cache. I have followed the
> methods called from the operate function in ruby.c
> (mh_memorytracer_possible_cache_miss, SimicsDriver::makeRequest,
> SimicsDriver::recordTransactionStats) and tried to see where the different
> stat counters are incremented. However, I don't see a "natural" place in the
> code I could add my own code to distinguish between different L1 caches.
> Could you enlighten me into this matter?
>
> Best Regards,
> Mladen
>
>
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