Re: [Gems-users] crossbar

["Mladen Nikitovic" <mladen@xxxxxxxxxxx>]

Hi,

Thank you for the quick answers. I question regarding the number of
switches: as it seems like the crossbar is configured as a three-stage
network, would it be possible to change the number of stages, for instance
only having two?

Regarding the ordered property, could you explain what you mean by
"point-to-point ordering" ? Is there a way to verify from the configuration
output whether the underlying topology is ordered or not? Or, is this a
natural property of each topology?

Regards,
Mladen

-----Original Message-----
From: gems-users-bounces@xxxxxxxxxxx [mailto:gems-users-bounces@xxxxxxxxxxx]
On Behalf Of Mike Marty
Sent: den 23 april 2007 16:40
To: Gems Users
Subject: Re: [Gems-users] crossbar


> I would like to have a better understanding of the crossbar model 
> using the MSI_MOSI_CMP_directory protocol. I did a simulation with 4 
> processor-configuration.
>
> Firstly, under "Network Configuration" it states that the network is a 
> SIMPLE_NETWORK and that the topology is a CROSSBAR. However, a number 
> of virtual_net_0/1/2/3/4 are mentioned that are either ordered or 
> unordered. Could you give a brief explanation of what this is and why 
> some are ordered and others unordered? What does it mean that a 
> virtual_net is ordered/unordered?
>

The ordered="true" property enforces point-to-point ordering regardless of
the underlying topology.  If the underlying topology is ordered, then this
option has no effect.

> Secondly, statistics show (under "Network stats") utilization for 
> switch_0 until switch_12, so there are 13 (0 until 12) switches in 
> total. It seems like there is one top-switch (Nr 12) that all are 
> connected to, right? Does this mean that there is a hierarchy? I fail 
> to understand how these switches are organized from a topology point 
> of view. Is 13 switches really needed to connect 4 processors and L2? 
> If yes, could you explain how they are used/connected?
>

There is a switch at the endpoint of each processor and a switch at the
endpoint of each L2 bank.  Then there are the internal interconnect switches
dependent on topology.

> A final side note, I saw that the final four data from the last switch 
> only specified Control stats, whereas the rest of the switches had 
> both Data and Control. Is there a reason for this?
>

Without seeing more info, I'm not sure

--Mike


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