Date: | Sat, 20 Jan 2007 16:57:21 +0200 |
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From: | "Shachar Gang" <shacharg@xxxxxxxxxxxxx> |
Subject: | [Gems-users] Adding delay of one cycle when a L1 cache is being accessed |
Hi, I am trying to add a delay of one cycle on an access to L1 cache, but what I want is the delay will be on special cases only (when a special bit is turned on in the accessed cache line) I already added the special bit in the AbstractCacheEntry.h file and the functions to change it in the CacheMemory class. I would like to know how the L1 access latency is being calculated - How can I change the sm file to add 1 cycle to the latency for every access I have to an L1 cache line that has my special bit turned on. Thanks for any help Shachar -- Open WebMail Project (http://openwebmail.org) |
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