[Gems-users] Tracking cache hits at instruction level

[Nikolas Galanis <nikolaos@xxxxxxxxxx>]

Hello,

I need to get cache statistics for each individual memory instruction 
(whether it is an L1 or an L2 hit or miss). I am using MOSI_SMB_bcast 
protocol. To do that I have put in pseq_t::mmuAccess() a function call 
to Sequencer.C (the call passes through OpalInterface.C using an 
intermediate function). The code of the function at Sequencer.c is:

myMemoryLevelHit_t Sequencer::memoryLevelHit(const Address& addr)
{
 assert(Protocol::m_TwoLevelCache);

 if ( 
m_chip_ptr->m_L1Cache_L1IcacheMemory_vec[m_version]->isTagPresent(line_address(addr)) 
)
   return L1I;
 if ( 
m_chip_ptr->m_L1Cache_L1DcacheMemory_vec[m_version]->isTagPresent(line_address(addr)) 
)
   return L1D;
 else if ( 
m_chip_ptr->m_L1Cache_cacheMemory_vec[m_version]->isTagPresent(line_address(addr)) 
)
   return L2;
 else
   return MAINMEM;
}


The modules compile without error, but when I load the modules I get the 
following error:

Ruby: ruby-opal link established. removing timing_model.
opalinterface: doing notify callback
Opal: opal-ruby link established.
OpalInterface: installation successful.
failed assertion 'm_size != 0' at fn TYPE& Vector<TYPE>::ref(int) [with 
TYPE = CacheMemory<L1Cache_Entry>*] in ../common/Vector.h:167
failed assertion 'm_size != 0' at fn TYPE& Vector<TYPE>::ref(int) [with 
TYPE = CacheMemory<L1Cache_Entry>*] in ../common/Vector.h:167

Do you have any idea why this is happening?

Also, does the way I am trying to get the statistics appear correct?

Thanks in advance,

Nikolas