Re: [Gems-users] cache stats

[Mladen Nikitovic <mladen@xxxxxx>]

Ok, thanks for the confirmation.

Regarding L2, I was previously instructed to modify 
addPrimaryStatSample() in Profiler.C/h to track the misses. But, someone 
also pointed to the doRequest function. Which function would be the best 
in order to track L2 misses/hits on per processor basis?
I'm confused regarding how to confirm the numbers. Previously, I was 
told that the profiler is presented with a request multiple times and 
therefore the stats that come out of it is not a good reference. But if 
I actually go ahead with modifying addPrimaryStatSample - which is a 
part of the profiler, wouldn't that give me wrong numbers? Is there 
something in the ordinary statistics that I can use to verify that my 
own numbers are correct?
I'm also interested in tracking the number of performed cache 
replacements. I would appreciate if someone could help me point to the 
files/functions that are related to this as I was unable to find them.
Best regards,
Mladen

Mike Marty wrote:
> It makes sense to make.  Make sure the REMOVE_DCACHE_FAST_PATH flag is 
> set to false
> --Mike
>
>
> Mladen Nikitovic wrote:
>   
> > Can anyone confirm this? Or, have anyone done this previously?
> >
> > Would be very thankful for some feedback.
> >
> > Regards,
> > Mladen
> >
> > Mladen Nikitovic wrote:
> >   
> >     
> > > Hi,
> > >
> > > Just want to verify with you if my approach to capture L1 and UL2 cache 
> > > statistics on a per-processor basis. Below is my augmented makeRequest 
> > > from the Sequencer.C file. Assuming that I have declared the vectors 
> > > correctly, would you say that this captures the accesses and hits 
> > > correctly? Don't know yet how to get the UL2 hits and misses though...
> > > I'm using MSI_MOSI_CMP_directory protocol  (GEMS 1.2)
> > >
> > > Regards,
> > > Mladen
> > >
> > > // Called by Driver (Simics or Tester).
> > > void Sequencer::makeRequest(const CacheMsg& request) {
> > >   int cpu = 
> > > m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version;
> > >  
> > >   assert(isReady(request));
> > >   bool write = (request.getType() == CacheRequestType_ST) ||
> > >     (request.getType() == CacheRequestType_ST_XACT) ||
> > >     (request.getType() == CacheRequestType_LDX_XACT) ||
> > >     (request.getType() == CacheRequestType_ATOMIC);
> > >
> > >   if (TSO && (request.getPrefetch() == PrefetchBit_No) && write) {
> > >     assert(m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->isReady());
> > >     m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->insertStore(request);
> > >     return;
> > >   }
> > >
> > >   bool hit = doRequest(request);
> > >  
> > >   if(request.getType() == CacheRequestType_IFETCH) /* IL1 access */
> > >     {
> > >       perProcessorIL1Access[cpu]++;
> > >       if(hit)
> > >     perProcessorIL1Hit[cpu]++;
> > >     }
> > >   else /* DL1 access */
> > >     {
> > >       perProcessorDL1Access[cpu]++;
> > >       if(hit)
> > >     perProcessorDL1Hit[cpu]++;
> > >       else
> > >     perProcessorUL2Access[cpu]++;
> > >     }
> > > }
> > >
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