Re: [Gems-users] Cache Miss Rate

["Carole-Jean Wu" <carolewu@xxxxxxxxxxxxx>]

Hello Greg,

Thanks a lot for your explanation. One last question is .. then .. L1 hit  = Data Request - L1 Misses - Fast Path Hit Return, right?

-Carole

On Mon, Apr 14, 2008 at 11:05 AM, Greg Byrd <gbyrd@xxxxxxxx> wrote:

Instruction references are likely zero because you have
"instruction-fetch-mode" set to "no-instruction-fetch".  This is a
time-saving mechanism for simulations -- Simics simply fetches
instruction directly from memory without sending those references to the
timing model (Ruby).

I believe the "requests missed" refers to fast path misses.  If you have
fast path enabled, then the sequencer will look for an L1-cached block
containing the requested address.  If it's in the L1 cache and the state
is compatible, then the sequence will immediately return the value as a
hit, without sending a CacheMsg to the L1Cache component.  If it can't
find the block, or if it is in the wrong state, then it's considered a
"fast path miss" and is send to the L1Cache.  You should refer to the
cache statistics to get an accurate count of misses, but if the fast
path is enabled, then the fast path hits should be added to the hits
that are reported by the L1Cache statistics.

I'm not sure if "data requests" includes the other categories in the
list (e.g., are prefetches included in that number?  atomic load
accesses?)  Someone else will have to answer that, or you can probably
figure it out by looking at the Sequencer code.

...Greg



Carole-Jean Wu wrote:

> Hello Greg,
>
> Thanks for  pointing me to Simics Driver Transaction Stats... I still
> have a few questions in regards to putting all these different
> statistics together.
> First,
> Insn requests is 0 because instructions don't go to this cache?
> Does "Data requests"represent total number of memory references?
> Do "Request missed: 2204349" mean number of transaction misses and
> "Hit return: 2101875" mean number of hit transactions?
> Then miss rate is going to be "Request missed / Data requests" and is
> 1.62%?
>
> Thanks a lot for your help!!
> Carole
>
>
> Simics Driver Transaction Stats
> ----------------------------------
> Insn requests: 0
> Data requests: 135717701
> Memory mapped IO register accesses: 0
> Device initiated accesses: 2565
> Other initiated accesses: 0
> Atomic load accesses: 65650
> Exceptions: 949759
> Non stallable accesses: 133408546
> Prefetches: 104806
> Cache Flush: 0
>
>
> Simics Driver Transaction Results Stats
> ------------------------------------------
> Fast path: 0
> Request missed: 2204349
> Sequencer not ready: 0
> Duplicate instruction fetches: 0
> Hit return: 2101875
> Atomic last accesses: 91910
>
> _________________________________________________________________________________________
> Ruby Statistics
>
> Total_misses: 2204349
> total_misses: 2204349
> user_misses: 1169397
> supervisor_misses: 1034952
> instruction_executed: 141136231588
> cycles_per_instruction: 0.5095
> misses_per_thousand_instructions: 0.0156186
> _________________________________________________________________________________________
>
> On Mon, Apr 14, 2008 at 10:04 AM, Greg Byrd <gbyrd@xxxxxxxx

> <mailto:gbyrd@xxxxxxxx>> wrote:
>
>     See the "Simics Driver Transaction Stats."
>
>     You'll see instruction requests and data requests, etc.
>
>     ...Greg
>
>
>     Carole-Jean Wu wrote:
>     > Hello GEMS-users,
>     >
>     > I am looking at the ruby dump-stat file (the long one) and couldn't
>     > figure out how many memory references there are to the cache.
>     >
>     > There are
>     >
>     > total number of instructions per chip
>     > total number of misses
>     > misses per thousand instruction
>     >
>     >
>     > but none of these tells me total number of memory references to
>     the cache.
>     >
>     > Can someone explain how they calculate this number or hit/miss rate?
>     >
>     > Thanks,
>     > Carole
>     >
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