Re: [Gems-users] question about LX_CACHE_NUM_SETS_BITS parameter

["Konstantinos Aisopos" <kaisopos@xxxxxxxxx>]

Yep, it's pretty confusing. What is actually even more confusing is
that this variable (L2_CACHE_NUM_SETS_BITS) changes, once I initialize
ruby, to its "per core" value! In other words, i set it as 16 and
right after initialization i find out that it's 10
[10=16-log(num_cores)]

simics> ruby0.setparam L2_CACHE_NUM_SETS_BITS 16

simics> ruby0.init
Ruby Timing Mode
Creating event queue...
Creating event queue done
Creating system...
  Processors: 64
Creating system done
Ruby initialization complete

simics> ruby0.listparam
L2_CACHE_NUM_SETS_BITS  : 10

anyway, i think it's clear to me now. Thanks Mike.

-Kostas

On Mon, Apr 21, 2008 at 11:01 AM, Mike Marty <mike.marty@xxxxxxxxx> wrote:
> RubyConfig.C will take the specified L2 parameters and divide it by the
> number of banks per chip.  So right now, the L2 size is specified for the
> entire chip (spanning several shared banks).  If you prefer specifying the
> L2 size per bank, comment out the single line of code in RubyConfig.C.  In
> retrospect, doing it this way was probably a bad decision and leads to
> confusion.
>
> --mike
>
>
>
>
> On Sun, Apr 20, 2008 at 9:22 PM, Konstantinos Aisopos <kaisopos@xxxxxxxxx>
> wrote:
> > thanks Mike. does the same happen with L2? If yes, isn't the default
> > value huge?? 16MB L2 per core?
> >
> > L2_CACHE_ASSOC 4
> > L2_CACHE_NUM_SETS_BITS 16
> > => L2 size = 2^16 * 4 * 64 = 16MB
> >
> > thanks,
> > Kostas
> >
> >
> >
> >
> > On Sun, Apr 20, 2008 at 10:10 PM, Mike Marty <mike.marty@xxxxxxxxx> wrote:
> > > If L1_CACHE_ASSOC is 4 and L1_CACHE_NUM_SETS_BITS is 8, then each L1
> cache
> > > instance is 2^8 * 4 * 64 bytes
> > >
> > >
> > >
> > >
> > > On Sun, Apr 20, 2008 at 1:26 PM, Konstantinos Aisopos
> <kaisopos@xxxxxxxxx>
> > > wrote:
> > > >
> > > >
> > > >
> > > > hi all,
> > > >
> > > > I have a quick question about some configuration parameters. I
> > > > simulate a MESI_SCMP protocol with 64 cores on one single chip.
> > > >
> > > > my question is: if LX is L1 or L2 and we have these parameters:
> > > > LX_CACHE_ASSOC 4
> > > > LX_CACHE_NUM_SETS_BITS 8
> > > > do these parameters represent the "total LX cache capacity" or the
> > > > "per core LX cache capacity"?
> > > >
> > > > in other words is the size of LX *per core*..
> > > >       4 * 2^16 = 256K entries => 256K * 64bytes/line = 16MB???
> > > > or.. (4 * 2^16) / 64 = 4K entries  => 4K * 64bytes/line = 256KB???
> > > >
> > > > thanks,
> > > > -Kostas
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