Other processors can still be rescheduled by the OS to run background
tasks. It could also be possible if you don't run your simulation for a
long time that the other threads haven't even reached the idling loop
yet.
Regards,
Dan
张量 wrote:
Hi,everyone!
I'm using gems-2.0 and MESI_SCMP_bankdirectory coherence protocol.
I want to check the conflicts in shared L2 cache.
First I run gzip on one of the 16 processors ( processor 5 ,in my
configuration) and let the other 15 processors run idle
function :
while(1){
asm volatile ("srl %g0, 0, %g0");
}
I believe that only L1 on P5 should send request to the shared L2,
but I find that all L1s keep sending requests (L1_GETS,L1_GETX . . ) to
L2 frequently , that's very confusing!
Why?
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