Date: | Sat, 12 Jul 2008 10:43:00 +0800 (CST) |
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From: | llccdd1985@xxxxxxx |
Subject: | Re: [Gems-users] why I can not get the result |
Hi, I use these command as below:
ot@localhost MOESI_CMP_token]# export SIMICS_EXTRA_LIB=./modules/
[root@localhost MOESI_CMP_token]# ./simics -stall Checking out a license... done: academic license. +----------------+ Copyright 1998-2007 by Virtutech, All Rights Reserved | Virtutech | Version: Simics 3.0.31 | Simics | Build: 1406 Host: x86-linux +----------------+ www.simics.com "Virtutech" and "Simics" are trademarks of Virtutech AB Use of this software is subject to appropriate license.
Type 'copyright' for details on copyright. Type 'help help' for info on the on-line documentation. simics> read-configuration exper.checkpoint
also the yellow console appears.
simics> instruction-fetch-mode instruction-cache-access-trace simics> istc-disable Turning I-STC off and flushing old data simics> dstc-disable Turning D-STC off and flushing old data simics> cpu-switch-time 1 The switch time will change to 1 cycles (for CPU-0) once all processors have synchronized. simics> load-module ruby successful installation of the ruby timing model. simics> load-module opal Queue registration cpu0 successful installation of the opal queue. hfa_init_local done: simics> ruby0.setparam g_NUM_PROCESSORS 2 simics> ruby0.setparam g_NUM_MEMORIES 1 simics> ruby0.setparam g_PROCS_PER_CHIP 2 simics> ruby0.setparam g_MEMORY_SIZE_BYTES 2147483648 simics> ruby0.init Ruby Timing Mode Creating event queue... Creating event queue done Creating system... Processors: 2 Creating system done Ruby: ruby-opal link established. removing timing_model. OpalInterface: installation successful. Ruby initialization complete simics> opal0.init pstate_t: warning: control register #0 == "(null)" has simics name "g0". pstate_t: warning: control register #1 == "(null)" has simics name "g1". pstate_t: warning: control register #2 == "(null)" has simics name "g2". pstate_t: warning: control register #3 == "(null)" has simics name "g3". pstate_t: warning: control register #4 == "(null)" has simics name "g4". pstate_t: warning: control register #5 == "(null)" has simics name "g5". pstate_t: warning: control register #6 == "(null)" has simics name "g6". pstate_t: warning: control register #7 == "(null)" has simics name "g7". pstate_t: warning: control register #8 == "(null)" has simics name "o0". pstate_t: warning: control register #9 == "(null)" has simics name "o1". pstate_t: warning: control register #10 == "(null)" has simics name "o2". pstate_t: warning: control register #11 == "(null)" has simics name "o3". pstate_t: warning: control register #12 == "(null)" has simics name "o4". pstate_t: warning: control register #13 == "(null)" has simics name "o5". pstate_t: warning: control register #14 == "(null)" has simics name "o6". pstate_t: warning: control register #15 == "(null)" has simics name "o7". pstate_t: warning: control register #16 == "(null)" has simics name "l0". pstate_t: warning: control register #17 == "(null)" has simics name "l1". pstate_t: warning: control register #18 == "(null)" has simics name "l2". pstate_t: warning: control register #19 == "(null)" has simics name "l3". pstate_t: warning: control register #20 == "(null)" has simics name "l4". pstate_t: warning: control register #21 == "(null)" has simics name "l5". pstate_t: warning: control register #22 == "(null)" has simics name "l6". pstate_t: warning: control register #23 == "(null)" has simics name "l7". pstate_t: warning: control register #24 == "(null)" has simics name "i0". pstate_t: warning: control register #25 == "(null)" has simics name "i1". pstate_t: warning: control register #26 == "(null)" has simics name "i2". pstate_t: warning: control register #27 == "(null)" has simics name "i3". pstate_t: warning: control register #28 == "(null)" has simics name "i4". pstate_t: warning: control register #29 == "(null)" has simics name "i5". pstate_t: warning: control register #30 == "(null)" has simics name "i6". pstate_t: warning: control register #31 == "(null)" has simics name "i7". pstate_t: warning: control register #99 == "(null)" has simics name "ecache_error_enable". pstate_t: warning: control register #100 == "(null)" has simics name "asynchronous_fault_status". pstate_t: warning: control register #101 == "(null)" has simics name "asynchronous_fault_address". pstate_t: warning: control register #102 == "(null)" has simics name "out_intr_data0". pstate_t: warning: control register #103 == "(null)" has simics name "out_intr_data1". pstate_t: warning: control register #104 == "(null)" has simics name "out_intr_data2". pstate_t: warning: control register #105 == "(null)" has simics name "out_intr_data3". pstate_t: warning: control register #106 == "(null)" has simics name "out_intr_data4". pstate_t: warning: control register #107 == "(null)" has simics name "out_intr_data5". pstate_t: warning: control register #108 == "(null)" has simics name "out_intr_data6". pstate_t: warning: control register #109 == "(null)" has simics name "out_intr_data7". Ruby: ruby-opal link established. removing timing_model. opalinterface: doing notify callback Opal: opal-ruby link established. OpalInterface: installation successful. simics> opal0.sim-start "result.opal" [0] PC 0x1048788 NPC 0x104878c ctx 0x0 [1] PC 0x1048d30 NPC 0x1048d34 ctx 0x0 simics>c after this I start to simulate,but when I interrupt the simualte,i also get many attributes that were 0,the cache miss also is 0,the result as below: L1D_cache cache stats:
L1D_cache_total_misses: 0 L1D_cache_total_demand_misses: 0 L1D_cache_total_prefetches: 0 L1D_cache_total_sw_prefetches: 0 L1D_cache_total_hw_prefetches: 0 L1D_cache_misses_per_transaction: 0 L1D_cache_misses_per_instruction: 0 L1D_cache_instructions_per_misses: NaN L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
L1I_cache cache stats:
L1I_cache_total_misses: 0 L1I_cache_total_demand_misses: 0 L1I_cache_total_prefetches: 0 L1I_cache_total_sw_prefetches: 0 L1I_cache_total_hw_prefetches: 0 L1I_cache_misses_per_transaction: 0 L1I_cache_misses_per_instruction: 0 L1I_cache_instructions_per_misses: NaN L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
L2_cache cache stats:
L2_cache_total_misses: 0 L2_cache_total_demand_misses: 0 L2_cache_total_prefetches: 0 L2_cache_total_sw_prefetches: 0 L2_cache_total_hw_prefetches: 0 L2_cache_misses_per_transaction: 0 L2_cache_misses_per_instruction: 0 L2_cache_instructions_per_misses: NaN L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
I use gems to statistic the cache miss,But I can not get the result,who can tell me the reason?thanks 渊波阔宅 湖景人生 |
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