[Gems-users] Couple of questions

[Arkaprava Basu <basu@xxxxxxxxxxx>]

Hi All,

           For my project I need to know about couple of following things,

1> I need to know about how can we modify the access latency and 
bandwidth of the main memory. Any leads on what are the function calls 
to the memory controllers, will be helpful too. I also need to have two 
different latency and b/w for two different portions of the physical 
memory. Any idea on how to achieve this?
2> I need to invalidate few specific cache blocks in the cache hierarchy 
( in both L1 and L2) in case of a particular event in the system. Any 
idea on how can I accomplish this?

Thank you,

Arka