Hi all,
I am studying MOESI_CMP_directoy protocol and encountered
some problems:
(1)I found that NodeID which stands for the processor
number is of type int, while m_version included in CacheMsg structure also
means the instance of the sequencer. In a 16-p CMP systems just integrated in a
single chip, for a specified cpu, is the
processor's NodeID equals to the corresponding m_version?
(2)In MOESI_CMP_directory-L2cache.sm. Some transition codes
really puzzled me:
transition(NP, {L1_PUTS, L1_PUTX, L1_PUTO})
{ ll_writebackNack;
o_popL1RequestQueue; }
I think the NP state of L2cache may
means that there is no valid cache block of some specified address on chip.
So how does the L1_PUTS produced? Meanwhile,
what is the "ll_writebackNack" action used for here?
Thanks in advance!
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