Re: [Gems-users] ATMTP "unrecognized instruction" error

[Daniel Nussbaum - Sun Microsystems - Burlington United States <dan.nussbaum@xxxxxxx>]

> Date: Thu, 22 Jan 2009 18:48:33 +0200
> From: Nikos Anastopoulos <anastop@xxxxxxxxxxxxxxxxx>
>
> Thanks very much for the quick reply!
>

No problem.

>
> Everything worked fine with the patch.
>

Excellent!

>
> Of course, until a new ld/st comes up :)
>

Please let me know if one does -- as you can see, these are really
easy to fix (if you have access to a SPARC architecture manual), but
I'd like to hear about it so that it's fixed in the next release.

Thanks.

dann

>
> Thanks,
>
> Nikos
>
>
> Daniel Nussbaum - Sun Microsystems - Burlington United States wrote:
> > Hi Nikos.
> >
> > Fuad Tabba (U. of Auckland -- cced) noticed this and several other
> > instruction-decoding problems / omissions.  We've made the
> > corresponding changes to our source base, but at this point, we
> > might not be publishing another release until sometime in the
> > spring.  Until then, you can apply the diffs below.
> >
> > Let us know if this solves your problem -- I'm pretty sure there
> > are additional LD and ST instructions that we don't yet recognize.
> > (I hope to do a clean-up pass for this kind of thing before the
> > next release.)
> >
> > Thanks.
> >
> > dann
> >
> >
> >> Date: Thu, 22 Jan 2009 18:18:34 +0200
> >> From: Nikos Anastopoulos <anastop@xxxxxxxxxxxxxxxxx>
> >>
> >> Hi,
> >> we are trying to use ATMTP to evaluate some TM code. We are
> >> building our binaries on a Niagara system using Sun Studio 12 (cc
> >> 5.9 SunOS_sparc 2007/05/03 ). We compiled with -m64 -mt
> >> -Wc,xarch=v9 , as specified in the rock-tm-test Makefile.
> >> However, in contrast to the rock-tm-test example, our program
> >> crashes with:
> >>
> >>   2 ERROR!!! tlb miss on unrecognized inst: d302a004 CPS bits not set
> >>
> >> We used gdb and found out that this corresponds actually to a
> >> "ld" instruction. In Rock.h, only ldsb, ldsh, ldsw, ldub, lduh,
> >> lduw, ldx instructions are defined. Another "ld" instruction in
> >> the same part of the code gives an lduh opcode when masked with
> >> MEM_OP_MASK. However, the ld instruction in question, when masked
> >> with MEM_OP_MASK gives 0xc1000000, which is not defined in Rock.h
> >> and thus we get the "unrecognized inst." error. Moreover, we
> >> found an "st" instruction which again when masked with
> >> MEM_OP_MASK gives 0xc1200000, which will result in an
> >> "unrecognized inst".
> >>
> >> Has anyone experienced a similar problem? Could it be a problem
> >> with the version of our compiler? Are we missing something in the
> >> setup process?
> >>
> >> Thanks in advance.
> >>
> >> Kind regards,
> >>
> >> Nikos.
> >>
> >>
> >
> > --------------------
> > [diffs (to files in ${GEMS}/ruby/rock)]
> > ---------
> >
> > dn142869@dighton>cvs -q diff -u10 -w -r 1.22 Rock.C
> > Index: Rock.C
> > ===================================================================
> > RCS file: /lab/scale/cvsroot/GEMS2/ruby/rock/Rock.C,v
> > retrieving revision 1.22
> > retrieving revision 1.24
> > diff -u -1 -0 -w -r1.22 -r1.24
> > --- Rock.C	28 Mar 2008 19:37:33 -0000	1.22
> > +++ Rock.C	29 Dec 2008 19:43:32 -0000	1.24
> > @@ -279,27 +279,30 @@
> >      } else if (val == TRAP_FAST_DATA_MMU_MISS) {
> >        //
> >        // DTLB miss 0x68
> >
> >        if ((instruction & MEM_OP_MASK) == OPCODE_LDSB || // LDSB;
> >            (instruction & MEM_OP_MASK) == OPCODE_LDSH || // LDSH
> >            (instruction & MEM_OP_MASK) == OPCODE_LDSW || // LDSW
> >            (instruction & MEM_OP_MASK) == OPCODE_LDUB || // LDUB
> >            (instruction & MEM_OP_MASK) == OPCODE_LDUH || // LDUH
> >            (instruction & MEM_OP_MASK) == OPCODE_LDUW || // LDUW
> > -          (instruction & MEM_OP_MASK) == OPCODE_LDX     // LDX
> > +          (instruction & MEM_OP_MASK) == OPCODE_LDX  || // LDX
> > +          (instruction & MEM_OP_MASK) == OPCODE_LDD  || // LDD
> > +          (instruction & MEM_OP_MASK) == OPCODE_LDF     // LDF
> >            ) {
> >          xact_mgr->setCPS_ld(get_thread_no(cpu));
> >        } else if ((instruction & MEM_OP_MASK) == OPCODE_STB || // STB
> >                   (instruction & MEM_OP_MASK) == OPCODE_STH || // STH
> >                   (instruction & MEM_OP_MASK) == OPCODE_STW || // STW
> > -                 (instruction & MEM_OP_MASK) == OPCODE_STX    // STX
> > +                 (instruction & MEM_OP_MASK) == OPCODE_STX || // STX
> > +                 (instruction & MEM_OP_MASK) == OPCODE_STF    // STF
> >                   ) {
> >          xact_mgr->setCPS_st(get_thread_no(cpu));
> >        } else {
> >          cerr << "  " << proc_no
> >               << " ERROR!!! tlb miss on unrecognized inst: "
> >               << hex << instruction << dec
> >               << " CPS bits not set." << endl;
> >          ASSERT(0);
> >        }
> >        xact_mgr->setCPS_prec(get_thread_no(cpu));
> > dn142869@dighton>cvs -q diff -u10 -w -r 1.14 Rock.h
> > Index: Rock.h
> > ===================================================================
> > RCS file: /lab/scale/cvsroot/GEMS2/ruby/rock/Rock.h,v
> > retrieving revision 1.14
> > retrieving revision 1.18
> > diff -u -1 -0 -w -r1.14 -r1.18
> > --- Rock.h	28 Mar 2008 19:37:23 -0000	1.14
> > +++ Rock.h	29 Dec 2008 19:43:32 -0000	1.18
> > @@ -77,25 +77,28 @@
> >
> >
> >  #define MEM_OP_MASK 0xc1f80000
> >  #define OPCODE_LDSB 0xc0480000 // LDSB
> >  #define OPCODE_LDSH 0xc0500000 // LDSH
> >  #define OPCODE_LDSW 0xc0400000 // LDSW
> >  #define OPCODE_LDUB 0xc0080000 // LDUB
> >  #define OPCODE_LDUH 0xc0100000 // LDUH
> >  #define OPCODE_LDUW 0xc0000000 // LDUW
> >  #define OPCODE_LDX  0xc0580000 // LDX
> > +#define OPCODE_LDD  0xc1180000 // LDD
> > +#define OPCODE_LDF  0xc1000000 // LDF
> >
> >  #define OPCODE_STB  0xc0280000 // STB
> > -#define OPCODE_STH  0xc0380000 // STH
> > +#define OPCODE_STH  0xc0300000 // STH
> >  #define OPCODE_STW  0xc0200000 // STW
> >  #define OPCODE_STX  0xc0700000 // STX
> > +#define OPCODE_STF  0xc1200000 // STF
> >
> >  #define OPCODE_FAIL 0x91d0300f // TA  %xcc, %g0 + 15
> >
> >  #define TRAP_ASYNC_ERROR        0x040
> >  #define TRAP_VECTORED_INT       0x060
> >  #define TRAP_FAST_DATA_MMU_MISS 0x068 // DTLB miss
> >  #define TRAP_SOFTWARE_TRAP      0x100 // tcc 0
> >  #define TRAP_ESOFTWARE_TRAP     0x1ff // tcc 0xff
> >
> >
> > @@ -131,21 +134,21 @@
> >  #define ATMTP_MEMBAR_OPCODE_MASK     (0xc1f80000)
> >  #define ATMTP_MEMBAR_OPCODE          (0x81400000)
> >
> >  // Bit 24 selects between UDIVX and SDIVX, but since we want the
> >  // same handler for both, we ignore it.
> >  #define ATMTP_DIV_OPCODE_MASK        (0xc0f80000)
> >  #define ATMTP_DIV_OPCODE             (0x80680000)
> >
> >  // Bit 23 selects between LDSTUB and LDSTUBA, but since we want the
> >  // same handler for both, we ignore it.
> > -#define ATMTP_LDSTUB_OPCODE_MASK     (0xc1b80000)
> > +#define ATMTP_LDSTUB_OPCODE_MASK     (0xc1780000)
> >  #define ATMTP_LDSTUB_OPCODE          (0xc0680000)
> >
> >  #define ATMTP_SAV_REST_OPCODE_MASK   (0xc1f80000)
> >  #define ATMTP_SAV_OPCODE             (0x81e00000)
> >  #define ATMTP_REST_OPCODE            (0x81e80000)
> >
> >  // Bit 20 selects between CASA and CASXA, but since we want the same
> >  // handler for both, we ignore it.
> >  //
> >  #define ATMTP_CASA_CASXA_OPCODE      (0xc1e00000)
> > dn142869@dighton>
> >
>