Hi all,
I have booted 4-core CMP system, each one has a thread
binded onto it to run the SPLASH benchmark binaries(./barnes <
input_4p.8192). After running for some cycles, I want to
copy the architectual state from one core to another(For example, from
core-0 to core-2) So it appears to me that the system has two redundant thread
except PID and some device infomation. I have modified the RUBY code to bypass
the supervisor memory access, so at this point I suppose the workload running of
the two threads are just the same.
But how can I copy the architectual state from one
core to another? Is it possibly implemented in simics+GEMS ?
Is there anyone who has done some similar
work ?
Any help is appreciated.
Regards,
shuchang
|