Date: | Mon, 7 Sep 2009 14:40:56 -0400 |
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From: | Edward Lee <edwl202@xxxxxxxxx> |
Subject: | [Gems-users] L2 Cache Miss rate |
Hi all, I have a little confusion about the ruby stats regarding the L2 Cache accesses and correspondingly calculating the L2 Cache Miss rate. For example, below is a copy of the stats file from an FFT benchmark (based on MOESI_SMP_directory protocol). As I checked earlier posts, total number of memory accesses is the sum of Insn requests and Data requests: (356241870 + 76057261) = 432299131. I am interested in calculating the L2 cache miss rate. So, by just dividing the L2_cache_total_misses: 138053 to total memory accesses gives me the miss rate? I suspect this would be incorrect as inst. requests dominate this total number of memory accesses but thats rarely used in L2 cache requests. So, how can I isolate the L2 Cache accesses here? Can anybody help me on this? Thanks, Ed ----------------------- Selected parts of the stats file ------------------------------------- L1D_cache cache stats: L1D_cache_total_misses: 2117964 L1D_cache_total_demand_misses: 2117964 L1D_cache_total_prefetches: 0 L1D_cache_total_sw_prefetches: 0 L1D_cache_total_hw_prefetches: 0 L1D_cache_misses_per_transaction: 2.11796e+06 L1D_cache_misses_per_instruction: 0.00594529 L1D_cache_instructions_per_misses: 168.2 L1D_cache_request_type_LD: 97.3424% L1D_cache_request_type_ST: 2.46463% L1D_cache_request_type_ATOMIC: 0.192921% L1D_cache_access_mode_type_SupervisorMode: 1987116 93.822% L1D_cache_access_mode_type_UserMode: 130848 6.17801% L1D_cache_request_size: [binsize: log2 max: 8 count: 2117964 average: 2.99419 | standard deviation: 2.2293 | 0 9343 1749447 10013 349161 ] L1I_cache cache stats: L1I_cache_total_misses: 485 L1I_cache_total_demand_misses: 485 L1I_cache_total_prefetches: 0 L1I_cache_total_sw_prefetches: 0 L1I_cache_total_hw_prefetches: 0 L1I_cache_misses_per_transaction: 485 L1I_cache_misses_per_instruction: 1.36143e-06 L1I_cache_instructions_per_misses: 734520 L1I_cache_request_type_IFETCH: 100% L1I_cache_access_mode_type_UserMode: 485 100% L1I_cache_request_size: [binsize: log2 max: 4 count: 485 average: 4 | standard deviation: 0 | 0 0 0 485 ] L2_cache cache stats: L2_cache_total_misses: 138053 L2_cache_total_demand_misses: 138053 L2_cache_total_prefetches: 0 L2_cache_total_sw_prefetches: 0 L2_cache_total_hw_prefetches: 0 L2_cache_misses_per_transaction: 138053 L2_cache_misses_per_instruction: 0.000387525 L2_cache_instructions_per_misses: 2580.48 L2_cache_request_type_LD: 69.8203% L2_cache_request_type_ST: 27.8929% L2_cache_request_type_ATOMIC: 2.06587% L2_cache_request_type_IFETCH: 0.22093% L2_cache_access_mode_type_SupervisorMode: 44311 32.0971% L2_cache_access_mode_type_UserMode: 93742 67.9029% L2_cache_request_size: [binsize: log2 max: 8 count: 138053 average: 7.00595 | standard deviation: 2.23386 | 0 6675 11351 5600 114427 ] Simics Driver Transaction Stats ---------------------------------- Insn requests: 356241870 Data requests: 76057261 Simics Driver Transaction Results Stats ------------------------------------------ Fast path: 73296358 Request missed: 2118449 |
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