Date: | Fri, 11 Sep 2009 12:08:13 -0400 |
---|---|
From: | sparsh mittal ISU <sparsh@xxxxxxxxxxx> |
Subject: | Re: [Gems-users] Regarding ruby speed |
Thanks a lot for kind explanation, I can understand your point. I tried these options to try to reduce the latency. As we see in simics user-guidef-for-unix. pdf; if timing model attached has no stall, then CPU does not stall. However, my observation is that some of these latencies cannot be set to zero (those which are still non-zero) , and for others, even after reducing their values to near-one, the ruby timing simulation takes almost same time. Is there a way or some specific parameter, which when being changed, may lead to speeding up of ruby? I would be grateful for your reply. read-configuration Baglewarm.conf instruction-fetch-mode instruction-fetch-trace dstc-disable istc-disable cpu-switch-time 10000 ; load-module ruby ruby0.setparam g_NUM_PROCESSORS 1 ruby0.setparam MEMORY_RESPONSE_LATENCY_MINUS_2 1 ruby0.setparam L1_RESPONSE_LATENCY 0 ruby0.setparam TIMER_LATENCY 1 ruby0.setparam L2_RESPONSE_LATENCY 0 ruby0.setparam L2_REQUEST_LATENCY 0 ruby0.setparam L1_REQUEST_LATENCY 0 ruby0.setparam CACHE_RESPONSE_LATENCY 0 ruby0.setparam L2_TAG_LATENCY 0 ruby0.setparam L2_RECYCLE_LATENCY 0 ruby0.setparam DIRECTORY_CACHE_LATENCY 1 ruby0.setparam DIRECTORY_LATENCY 1 ruby0.setparam NETWORK_LINK_LATENCY 1 ruby0.setparam SEQUENCER_TO_CONTROLLER_LATENCY 1 ruby0.setparam g_FIXED_TIMEOUT_LATENCY 1 ruby0.setparam MEM_CTL_LATENCY 5 ruby0.setparam g_FIXED_TIMEOUT_LATENCY 30 ruby0.setparam RECYCLE_LATENCY 1 ruby0.setparam COPY_HEAD_LATENCY 1 ruby0.setparam BANK_BUSY_TIME 2 ruby0.setparam_str PERIODIC_TIMER_WAKEUPS false ruby0.setparam g_think_time 1 ruby0.setparam g_hold_time 1 ruby0.setparam g_wait_time 1 ruby0.init ruby0.load-caches rubycache date; c 200000 ; date Thanks Sparsh On Thu, Sep 10, 2009 at 4:04 PM, Polina Dudnik <pdudnik@xxxxxxxxx> wrote: Well, if you want to simulate caches for multi-processor system, misses and hits statistics is entirely dependent on the coherence protocol. So, you can't do research on cache and ignore the coherence protocol. -- Thanks and Regards Sparsh Mittal Graduate Student Electrical and Computer Engineering Iowa State University, Iowa, USA |
[← Prev in Thread] | Current Thread | [Next in Thread→] |
---|---|---|
|
Previous by Date: | Re: [Gems-users] TM - runtime error, holey003 |
---|---|
Next by Date: | Re: [Gems-users] Regarding ruby speed, Polina Dudnik |
Previous by Thread: | Re: [Gems-users] Regarding ruby speed, Polina Dudnik |
Next by Thread: | Re: [Gems-users] Regarding ruby speed, Polina Dudnik |
Indexes: | [Date] [Thread] |