[Gems-users] How does the ruby L2 Cache get datalines and tags in simulation?except write-backs and miss-fetch.

[MaDafan <dafan_ma@xxxxxxxxxxx>]

Hi there,
Recently I'm doing some experiment about the L2cache-bank access diversion, the basic idea is to map the outstanding requests aimed at a certian masked bank to another bank on chip, I think It's doable just by adjusting address decoding mechnism, so I have modified several ruby files I thought relevant like Cachememory.h, abstractChip.h, Ruby_componentmapping.h, and the according slicc protocol files.
Assuming every access to the masked bank will be diverted to another L2 bank, the simulation should end up with no fault, but it fails because a L1_GETS access is supposed to hit in the masked bank, but diverted to a set in another bank, then no valid tag is found there, causing simulation fault.
 Actually the fault confuses me a lot, in my opinion, if the whole system started with cold vacuum cache, the masked bank will always be empty because datalines only go into L2 cache through write-backs from L1Cache or L2 TBEtable which should have been diverted! to another bank, right? If not, there should be something like L2 cache prefetcher in ruby which directly load datalines from memory, or L2 cache filling mechanism in initialization, but I can not find any clue.
Can anyone enlignten me about my problem? I'll appreciate that very much!
(The protocol I use is MOESI_CMP_directory)
Thx!

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