[Gems-users] CMP shared L2 cache?

[Chien-chih Liao <nicky1216@xxxxxxxxx>]

Hi:

When I was looking into the GEMS code, I am curious about the fact that CMP protocol has L2 cache shared by all processors in the same Chip. When the L1CacheController tries to create request message to L2 cache, the destination of the message will be the result of the function "map_L1CacheMachId_to_L2Cache", which is decided by the index of the L1 cache and the address (cache bank number). Thus, given a fixed L1 cache, it will only send its request to a specific L2 cache. If there are the same amount of L2 cache as L1, then how does all processors share all the L2 cache? It looks to me that one processor will rely on its private L1 cache, which in turn relies on its mapped L2 cache. If there is only one L2 cache in a Chip then it is trivial that L2 cache is shared among all the processors.

Another question is that I am confused about the two cache directories in one Chip...Chip class contains the Directory_directory_vec vector and also, L2Cache_localDirectory_vec. Do both directory vector used and how do them keep the state synchronized? What I saw is that L2CacheController operates on the L2Cache_localDirectory_vec but DirectoryController operates on the Directory_directory_vec...

My ultimate goal is to hack GEMS to have a "cooperative" private L2 caches in CMP so I really hope that I can fully understand how the CMP in GEMS works...I already spent much time on the code but still had these questions. I will really appreciate if anyone can give some hints on them...Thank you very much.

Best Regards

Nick