[Gems-users] Latency and number of memory request

["张轶" <zhangyi@xxxxxxxxxxxxxx>]

Hi all!

 

I have two questions about memory request in gems.

 

1.The first is about the memory request latency in gems.

In the simics, the cycle value is decided by the processor frequency, in other words, this value is not a fixed value. It seems that gems cycle is multiple of simics cycle. Is it to say if the processor frequency in the simulation changes, then the latency value of a memory request changes too?

 

2.On one processor, how many request a thread can issue at the same time?

In my simulation, I am using X86 arch and SMP protocal and simulate a 2 processor system. So there is no opal, then without pipeline and without out of order instruction. To my understanding, for such a simulation, in each processor each time there would issue two requests at the most(one is instruction cache miss the other is data cache miss). So totally, in my system there would have 4 requests waiting in the memory controller at the most. I have tried to print out all the memory requests in the simulation and found that at some time there would be at most 6 requests waiting in the memory controller.  So why?

 

Many thanks!

 

Zhang Yi