Re: [Gems-users] Regarding ruby miss rate

[sparsh mittal ISU <sparsh@xxxxxxxxxxx>]

Thanks a lot Dan.
So, is there an option, such as using long runs with warming, that we
can expect the miss rates to be somewhat same?
I appreciate your time and help.
Sparsh

On Tue, May 11, 2010 at 11:59 AM, Dan Gibson <degibson@xxxxxxxx> wrote:
> Out-of-order processors issue memory requests from false paths, and issue
> instruction fetch more aggressively, than in-order cores. Yes, the miss
> rates should be different, and should be noticeably different from short
> runs with cold caches.
> Regards,
> Dan
>
> On Tue, May 11, 2010 at 10:25 AM, sparsh mittal ISU <sparsh@xxxxxxxxxxx>
> wrote:
>>
>> Hello
>> Considering L2 miss rate to be (L2miss/L2access) or (L2miss/L1misses)
>> for both ruby+simics only and ruby+opal;
>> I am finding that the miss rates of L2 is different for ruby+simics
>> (doing c 100000) and ruby+opal (doing opal0.sim-step 100000).
>> May be it is a trivial question; but should the miss rates be
>> different. I would be grateful for some explanation.
>>
>> --
>> Thanks and Regards
>> Sparsh Mittal
>> Graduate Student
>> Electrical and Computer Engineering
>> Iowa State University, Iowa, USA
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>
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-- 
Thanks and Regards
Sparsh Mittal
Graduate Student
Electrical and Computer Engineering
Iowa State University, Iowa, USA