[Gems-users] Opal's execution of atomic instruction

[Muhammad abid Mughal <mabidm_pieas@xxxxxxxxx>]

hi , hope all guys doing good.If Opal takes more than one cycle to execute atomic instruction then it will feed wrong data to dependent loads via LSQ.Atomic inst gets executed in one cycle if  it always hit in WrtieBuffer or L1D$(if not using WriteBuffer).These comments apply to casa/casxa/ldstub/ldstuba.  E.g.

casa/casxa: this atomic inst conditionally swap destination register R[rd] and memory pointed by R[rs1].If condition is true then it swaps R[rd] with memory location else only updates R[rd] with memory location pointed by R[rs1].

             Suppose All regs of casa/casxa are ready and there is no hit in LSQ and WriteBuffer is Full : this condition will feed wrong data to dependent loads via LSQ if condition of casa/casxa is not true (this cond will be checked later when it hits in WriteBuffer).In other words for this cond casa/casxa works as if the cond is always true or as a swap/swapa.

I have made some corrections and would like to discuss if i get some response.

any comments about this?

Regards,

Muhammad abid