Hi all,
If I want to add some code to calculate false sharing miss, I need some information
about processor access address of cache line, and other processor write or read this
address of cache line. Are there some these information that by calling existing
function could be obtained ?
In ruby/slicc_interface/RubySlicc_Profiler_interface.C, there is a function
void profile_sharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner)
but I do not know what these parameters represent the meanning.
and I run the simulation using splash-2 benchmark on GEMS, but the output
the sharing miss always is zero. what's wrong ? Is it associated protocol ? MOSI_SMP_bcast or MSI_MOSI_CMP_directory or else ?
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AddressProfiler Stats
sharing_misses: 0
getx_sharing_histogram: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
gets_sharing_histogram: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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I turn on the parameters PROFILE_HOT_LINES: true and PROFILE_ALL_INSTRUCTIONS: true
but in ruby/profiler/Profiler.C
Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id) {
...
m_address_profiler_ptr->addTraceSample(msg.getAddress(), msg.getProgramCounter(), msg.getType(), msg.getAccessMode(), id, false);
}
the last argument always false, so the following function that if statement can't step in, is it a bug ?
void AddressProfiler::addTraceSample(Address data_addr, Address pc_addr, CacheRequestType type, AccessModeType access_mode, NodeID id, bool sharing_miss)
{
if (PROFILE_HOT_LINES) { if (sharing_miss) { m_sharing_miss_counter++; }
}
...
}
If someone knows it , please help me.
Thanks a lot for you help in advance. Mr. Li
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