[Gems-users] About memory latency for CMP

[junli gu <gujunli@xxxxxxxxx>]

Hey all:

  I am simulating a 16-core CMP using Simics+Ruby. First I know that the latency values are all ruby cycles, which means 1 ruby cycles equals to 2 CPU cycles. I am simulating a 16-core CMP using the default values as the following: 

NULL_LATENCY:                      1                     ; Shortest possible latency
ISSUE_LATENCY:                     2                     ; Latency to send out a request to the interconnect
CACHE_LATENCY:                     1                     ; Latency to source data from a cache to the interconnect
MEMORY_LATENCY:                    35                    ; Latency to source data from a memory module to the interconnect
DIRECTORY_LATENCY:                 1                     ; Latency of directory lookup
NETWORK_LINK_LATENCY:              1                     ; Latency for a single node-to-node hop in the interconnect
SEQUENCER_TO_CONTROLLER_LATENCY:   8                     ; Latency added by sequencer to requests to cache controller
TRANSITIONS_PER_RUBY_CYCLE:        32                    ; Maximum transitions per cycle for all SLICC state machines
SEQUENCER_OUTSTANDING_REQUESTS:    20                    ; Number of outstanding requests per sequencer

My questions are:

A) I am positive about the L2 cache latency and memory latency. It is supposed to be 10 and 35 ruby cycles, which means 20 and 70 cpu cycles. Am I right?

B)  are these numbers realistic? I mean do they match the ones are in real products? 

C) For big cores like 16-core or even 32-core, how should these numbers change?  I guess when we have more cores the inter connection latency and memory latency will also increase?  Also I am not sure whether NETWORK_LINK_LATENCY:              1     is too small.

Thank you in advance!

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Junli Gu--谷俊丽
Coordinated Science Lab
University of Illinois at Urbana-Champaign
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