Re: [Gems-users] MOESI_CMP_directory

[Dave <zhu_dave@xxxxxxxxx>]

Is MOESI_CMP_directory protocol more AMD-like? I mean the protocols in dual-core AMD systems? If not, what could be an example system?

Thanks. 

Mike Marty <mikem@xxxxxxxxxxx> wrote:
>  
> > -By looking at the source code (e.g. MOESI_CMP_directory-L1cache.sm), I see there is neither Exclusive nor Invalid state implemented. Why is that?
>
> Idle == Invalid
>
> The E-state is implemented as M and MM.  An exclusive response goes from
> IS-->M.  A store then transitions to MM.
>
> > -There is no transient state to the extra states M_W, MM, and MM_W. Are the extra states never used?
>
> M_W and MM_W are "waiting" states to ensure that a processor is able to
> use the block before using permissions.  They really aren't needed for the
> protocol because the blocking logic accomplishes the same thing, but I
> added
>  them to be consistent with MOESI_CMP_token
>
> > -Is there a state transition diagram for the MOESI_CMP_directory protocol? It would really help to understand the protocol and the source code.
>
> Sorry, no state-transition diagram.
>
> > -It is said that this protocol uses non-inclusive L1/L2 caching with blocking caches. Could somebody please elaborate?
> >
>
> A cache "blocks" when handling a request.  Therefore subsequent requests
> are queued up instead of NACKed.
>
> --Mike
>
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