Re: [Gems-users] Atomic operation implementation

["hongxia sun" <sunhx.seraph@xxxxxxxxx>]

Dan,

 

Thank you for your help!

 

But there are still some questions on this topic. I looked up in SIMICS doc and found some explanation about Atomic Instruction in simics-micro-architectual-interface. It said that "MAI handles this by locking a ram region at a configurable granularity when the first access is issued. The lock is released as soon as the second access is finished or if the instruction is squashed. Any conflicting transaction to the same memory region issued between the two by any processor will stall until the lock is released." Does it means any atomic operation is handled by SIMICS itself? SIMICS will control the conflicting memory accesses between multiprocessors? Is it best to set the lock granularity as the size of a cache line?

 

I know that in our currently simulation, we need to do nothing special to support atomic operation. However, in a real system, no such mechanism to control atomic operation between multiprocessors. For example, in MIPS, it implements spin lock through LL-SC. All the processors can try LL-SC to acquire the lock, and they will check whether there are any other stores between their own LL-SC by some special hardware themselves. Is it still nothing to do with Cache Coherence Protocol? Do we still need not to add any special mechanism in Cache Coherence Protocol to support such atomic instructions?
 

Thanks a lot!

 

Best Regards,

Hongxia
 

2006/10/18, Dan Gibson <degibson@xxxxxxxx>:

Hongxia,

GEMS (Ruby in particular) treats all ATOMIC-type operations as stores, with the exception of LDDA. Also, Simics only allows the FIRST member of an atomic action to stall, though both will appear to Ruby in the same "cycle" -- that is, a read-modify-write operation may appear to Ruby as two atomics in a row, but only the first will be stallable and therefore the operations will occur atomically.

In short, there is no need to make a special modification to your protocol to support the regular set of atomics provided by UltraSPARC III+.

Regards,
Dan Gibson

hongxia sun wrote:

Dear all,

 

In our recently simulation on GEMS, we are trying to implement our protocol based on MSI_MOSI_CMP_directory protocol.

 

We found there was a "CacheRequestType:ATOMIC" can come from mandatory queue which communicated with processor, but no actual support on such atomic operation in protocol.

 

We tried to support such atomic operation in our protocol. We wondered whether such atomic memory access was tranfer by SIMICS to RUBY through files in /ruby/simics/.

 

We noticed that in GEMS home page, the description of GEMS Key Features said "Leverages the power of Virtutech Simics to simulate a Sparc multiprocessor system. " Does it mean that GEMS only support Sparc atomic instruction? Or SIMICS can split atomic instructions of different processors into the same memory access operation to GEMS? How can we implement atomic operation in our protocol? Where could we start from?

 

Any help will be greatly appreciate!

Thank you!

 

Best Regards,

Hongxia Sun

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