[Gems-users] Cache access latency in SMP and CMP protocols

[lya755@xxxxxxxxxxxxxxxxxxxx]

Dear list,
 
I know this has probably been discussed before but after a search on the 
archive I haven't found a specific answer. In the SMP protocols, does ruby 
model different latency for accessing a private L2 cache and accessing an L2 
cache of another processor? Likewise, in CMP protocols, even if all processors 
share an L2, does ruby model different latency for accessing a bank that is 
physically closer and a bank that is physically farther? In summary, does ruby 
take into account the physical locations of L2 cache when deciding access 
latencies? 
 
Another question is, what is the easiest way to model a CMP system with a 
private L2 for each processor? If I start from the MOSI_SMP_bcast protocol, 
what should I be changing? I assume I have to specify that the processors are 
all on the same chip, but other than that are there significant changes to be 
made? Also, if I start from any of the CMP protocols, how do I assign the 
banks for each processor? 
 
Sorry for asking so many questions but your help is greatly appreciated!!
 
Thanks,
Lei



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