Re: [Gems-users] Cache access latency in SMP and CMP protocols

["Mike Marty" <mikem@xxxxxxxxxxx>]

> I know this has probably been discussed before but after a search on the
> archive I haven't found a specific answer. In the SMP protocols, does ruby
> model different latency for accessing a private L2 cache and accessing an 
> L2
> cache of another processor?
Yes.

> Likewise, in CMP protocols, even if all processors
> share an L2, does ruby model different latency for accessing a bank that 
> is
> physically closer and a bank that is physically farther? In summary, does 
> ruby
> take into account the physical locations of L2 cache when deciding access
> latencies?
Yes, the shared L2 can be split into multiple banks.  The physical latencies 
can be specified by the network topology.
> Another question is, what is the easiest way to model a CMP system with a
> private L2 for each processor? If I start from the MOSI_SMP_bcast 
> protocol,
> what should I be changing? I assume I have to specify that the processors 
> are
> all on the same chip, but other than that are there significant changes to 
> be
> made?
A CMP system with private L2s for each processor is pretty close to what our 
SMP protocols model.  Except our SMP protocols use a combined L1/L2 
controller.
> Also, if I start from any of the CMP protocols, how do I assign the
> banks for each processor?
You would change how L1 request messages are sent to a cache bank.  You can 
define a different mapping function.  For example, instead of 
map_L1CacheMachId_to_L2Cache, maybe define 
map_L1CacheMachId_to_PrivateL2Cache.