Re: [Gems-users] about MessageBuffer and Ports

[Enrique Vallejo Gutiérrez <enrique@xxxxxxxxxxxxx>]

Title: RE: [Gems-users] about MessageBuffer and Ports

Hi Dave Z.,

        The keyword "network" defines whether the port sends or receives messages from the network. Then, it can be “To” if it sends messages, or “From” if it receives messages from the network. In order to avoid deadlock, the network is divided into different virtual networks, this is, they share the same physical links, but they use different virtual channels. Depending on the details of the coherence protocol, a different number of virtual networks is needed. Usually on each of them a different type of message is sent (requests from a cache to a directory, replies from the directory, messages cache-to-cache, etc). The idea is to avoid a circular dependence in which, for example, requests on the head of a queue block needed replies, thus avoiding any further progress.

        Regarding data transfers between processors: There are some protocols in which this happens. Any protocol with “Owned” state will do that, in fact. The owner of a cache line is the responsible for the value of the cache line. Then, when a directory receives a request for a cache line (say a GETS), and a cache controller is the owner of that line, the directory controller will refer the message (on a different virtual network, to avoid deadlock) to the owner, and the owner will directly send the cache contents to the requestor cache (again, a different virtual network). As you see, obviously there is the need for the two buffers you mention, for sending and receiving data. For example, in MOESI_SMP_directory, the virtual network #2 is used for cache-to-cache transfers, and each cache has a MessageBuffer connected TO it (responseFromCache) and another one FROM it (responseToCache).

        Regarding the timing: The timing of the data transfer process is the same as the timing of processing the messages involved. Why would you need the message carrying the actual data? Obviously, this is a simulation artifact (to reduce memory usage), as it is not needed: it is Simics that holds the current data. The number of misses can be profiled from the number of requests to “Invalid” cache lines (only the state is needed, not the actual data)

Regards,

Enrique Vallejo

-----Mensaje original-----
De: gems-users-bounces@xxxxxxxxxxx [mailto:gems-users-bounces@xxxxxxxxxxx] En nombre de Dave Z.
Enviado el: martes, 19 de septiembre de 2006 1:30
Para: gems
Asunto: [Gems-users] about MessageBuffer and Ports

Hello All,

I am looking into how in_ports, out_ports, and

MessageBuffers are defined. In the *cache.sm file,

some message buffers are declared like MessageBuffer

requestFromCache, network="To", virtual_network="0".

Could somebody please expain what "network" and

"virtual_network" refer to?

Then, the input and output ports associated with the

message buffers are declared. With regard to my

previous question on direct data transfers between

processors, would it work if I create two message

buffers, one for sending messages and one for

receiving messages, create input ports and output

ports accordingly, define new message types, actions,

etc.?

As Ruby does not work with actual data, but only

models the timing of operations related with data, how

could I copy a cache line from one processor's cache

to another? I'm interested in the timing of the copy

process as well as the number of misses on the other

processor. So, it's important to copy the actual data

so that I can see the effects afterwards.

Thank you very much.

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