[Gems-users] Different cache line sizes?

[mehmetderin.harmanci@xxxxxxx]

 Hello all,

 As far as I have seen from the Ruby code, the cache line sizes for L1 and L2
 level caches are the same. Is it possible to have the L1 and L2 level cache
 line sizes different (without breaking down anything, e.g. sharing information
 in the directories)? Is protocol with shared L2 cache configuration suitable
for
 that (e.g. MSI_MOSI_CMP_directory)? I think of using a single chip ,taking the
 g_DATA_BLOCK_SIZE size of L1 level caches and another cache line size for L2
 level cache. Is that feasible or not?

 Thanks for your attention.

 Derin Harmanci