Re: [Gems-users] MOSI_SMP_bcast state transition error

[Mike Marty <mikem@xxxxxxxxxxx>]

At time 40, processor #0 sees it own GETX request:

40   0   0    L1Cache            Own_GETX  IM_AD>IM_D   [0x48c0, line 0x48c0]


However at time 45, another GETX from itself arrives for 0x48c0, 
generating an invalid transition.
--Mike



Niket Agarwal (niketa@xxxxxxxxxxxxx) wrote:
> Hi all, 
> I made some changes to the network code in ruby and tried running the MOSI_SMP_bcast with 4 processors in the tester with HIERARCHICAL_SWITCH as the network. I get the following error. Can anyone throw some light onto this.  
>
> Thanks, 
> Niket 
>
> Request trace enabled to output file 'ruby.trace.gz'
>       2   2  -1        Seq               Begin       >       [0x62c0, line 0x62c0]
>       4   2  -1        Seq               Begin       >       [0x38c0, line 0x38c0]
>       5   2   0    L1Cache               Store     NP>IM_AD  [0x62c0, line 0x62c0]
>       6   0  -1        Seq               Begin       >       [0x48c0, line 0x48c0]
>       7   2   0    L1Cache               Store     NP>IM_AD  [0x38c0, line 0x38c0]
>       8   1  -1        Seq               Begin       >       [0x5dc0, line 0x5dc0]
>       8   0   0    L1Cache               Store     NP>IM_AD  [0x48c0, line 0x48c0]
>      10   0  -1        Seq               Begin       >       [0x15c0, line 0x15c0]
>      12   3  -1        Seq               Begin       >       [0x2bc0, line 0x2bc0]
>      13   3   0    L1Cache               Store     NP>IM_AD  [0x2bc0, line 0x2bc0]
>      14   2  -1        Seq               Begin       >       [0x3c0, line 0x3c0]
>      16   1  -1        Seq               Begin       >       [0x47c0, line 0x47c0]
>      16   2   0    L1Cache               Store     NP>IM_AD  [0x3c0, line 0x3c0]
>      18   2  -1        Seq               Begin       >       [0x5dc0, line 0x5dc0]
>      19   1   0    L1Cache               Store     NP>IM_AD  [0x47c0, line 0x47c0]
>      20   0   0    L1Cache          Other_GETX     NP>NP     [0x62c0, line 0x62c0]
>      20   1  -1        Seq               Begin       >       [0x62c0, line 0x62c0]
>      22   0   0    L1Cache          Other_GETX     NP>NP     [0x62c0, line 0x62c0]
>      22   3  -1        Seq               Begin       >       [0x5cc0, line 0x5cc0]
>      22   2   0    L1Cache               Store     NP>IM_AD  [0x5dc0, line 0x5dc0]
>      23   0   0    L1Cache          Other_GETX     NP>NP     [0x62c0, line 0x62c0]
>      23   3   0    L1Cache               Store     NP>IM_AD  [0x5cc0, line 0x5cc0]
>      24   1   0    L1Cache               Store     NP>IM_AD  [0x62c0, line 0x62c0]
>      24   2  -1        Seq               Begin       >       [0x43c0, line 0x43c0]
>      26   0   0    L1Cache          Other_GETX     NP>NP     [0x62c0, line 0x62c0]
>      26   1  -1        Seq               Begin       >       [0x57c0, line 0x57c0]
>      28   1  -1        Seq               Begin       >       [0x2bc0, line 0x2bc0]
>      28   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      29   0   0    L1Cache          Other_GETX     NP>NP     [0x62c0, line 0x62c0]
>      30   2  -1        Seq               Begin       >       [0x57c0, line 0x57c0]
>      31   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      31   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      32   0   0    L1Cache          Other_GETX     NP>NP     [0x38c0, line 0x38c0]
>      32   0  -1        Seq               Begin       >       [0x440, line 0x440]
>      33   0   0    L1Cache          Other_GETX     NP>NP     [0x38c0, line 0x38c0]
>      33   0   0    L1Cache               Store     NP>IM_AD  [0x440, line 0x440]
>      34   1  -1        Seq               Begin       >       [0x13c0, line 0x13c0]
>      34   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      34   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      35   1   0    L1Cache               Store     NP>IM_AD  [0x13c0, line 0x13c0]
>      36   1  -1        Seq               Begin       >       [0x66c0, line 0x66c0]
>      36   2  -1        Seq               Begin       >       [0x66c0, line 0x66c0]
>      37   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      37   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      37   0   0    L1Cache          Other_GETX     NP>NP     [0x38c0, line 0x38c0]
>      38   0  -1        Seq               Begin       >       [0x5ac0, line 0x5ac0]
>      39   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      39   1   0    L1Cache              Ifetch     NP>IS_AD  [0x66c0, line 0x66c0]
>      40   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      40   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      40   0   0    L1Cache            Own_GETX  IM_AD>IM_D   [0x48c0, line 0x48c0]
>      40   3  -1        Seq               Begin       >       [0x440, line 0x440]
>      41   0   0    L1Cache               Store     NP>IM_AD  [0x5ac0, line 0x5ac0]
>      42   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      42   3  -1        Seq               Begin       >       [0x1dc0, line 0x1dc0]
>      43   0   0    L1Cache          Other_GETX     NP>NP     [0x38c0, line 0x38c0]
>      43   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      43   2   0    L1Cache            L1_to_L2  IM_AD>IM_AD  [0x62c0, line 0x62c0]
>      43   3   0    L1Cache               Store     NP>IM_AD  [0x440, line 0x440]
>      44   3  -1        Seq               Begin       >       [0x18c0, line 0x18c0]
>      44   3   0    L1Cache               Store     NP>IM_AD  [0x1dc0, line 0x1dc0]
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:707: m_id is 0
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:707: m_id is 0
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:708: m_version is 0
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:708: m_version is 0
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:709: g_eventQueue_ptr->getTime() is 45
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:709: g_eventQueue_ptr->getTime() is 45
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:710: addr is [0x48c0, line 0x48c0]
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:710: addr is [0x48c0, line 0x48c0]
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:711: event is Own_GETX
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:711: event is Own_GETX
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:712: state is IM_D
> Warning: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:712: state is IM_D
> Fatal Error: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:713: Invalid transition
> Fatal Error: in fn TransitionResult L1Cache_Controller::doTransitionWorker(L1Cache_Event, L1Cache_State, L1Cache_State&, const Address&) in generated/MOSI_SMP_bcast/L1Cache_Transitions.C:713: Invalid transition
> Aborted
>
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