Re: [Gems-users] 3 hop writeback MESI SCMP

[arrvindh shriraman <arrvindh_shriraman@xxxxxxxxx>]

That was a super quick reply for the first question
Q2) I see that in some of your recent papers (Ring ordering, MICRO 2006), you use a director cache or memory interface cache even for CMP systems. I am not entirely sure what the purpose or rational behind this cache is. In other words, what is the entry of a memory interface cache look like.

My understanding is if you have a 1 CMP system with shared L2 the entire directory  will be on-chip

-- Arrvindh

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