Hi,
I tried to implement a flushing mechanism for the caches by adding the
following method to the CacheMemory class.
template<class ENTRY>
inline
void CacheMemory<ENTRY>::Flush(void)
{
for (int i = 0; i < m_cache_num_sets; i++) {
for (int j = 0; j < m_cache_assoc; j++) {
m_cache[i][j].m_Address.setAddress(0);
m_cache[i][j].m_LastRef = 0;
m_cache[i][j].m_Permission = AccessPermission_NotPresent;
m_cache[i][j].m_CacheState = L1Cache_State_L1_I;
}
}
}
Now, in Chip.C I do the actual flushing:
void Chip::flushCache(int id)
{
m_L1Cache_L1IcacheMemory_vec[id]->Flush();
m_L1Cache_L1DcacheMemory_vec[id]->Flush();
}
If I only flush the L1 I-cache it seem to work, but when I do it
together with the L1 D-cache the simulator crashes.
simics> ruby0.flush-cache cpuNumber = 0
simics> c
failed assertion 'loc != -1' at fn ENTRY&
CacheMemory<ENTRY>::lookup(const Address&) [with ENTRY = L1Cache_Entry]
in system/CacheMemory.h:489
failed assertion 'loc != -1' at fn ENTRY&
CacheMemory<ENTRY>::lookup(const Address&) [with ENTRY = L1Cache_Entry]
in system/CacheMemory.h:489
At this point you might want to attach a debug to the running and get to the
crash site; otherwise press enter to continue
PID: 22541
Warning: Interrupt key pressed more than once.
Pressing it again will force Simics back to the command prompt.
This may corrupt the running simulation.
Try waiting for Simics to stop first.
Does anyone have an idea on what the problem might be? Has anyone tried
to flush the caches before?
Regards,
Mladen
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