Re: [Gems-users] cache flushing

[Mladen Nikitovic <mladen@xxxxxx>]

Hi,

right, that makes sense. I didn't shutdown the processor at that time, 
so I can imagine the scenario that you described.
I have a follow up-question: If I want to simulate the side-effects of a 
processor shutdown by flushing the context of all buffers and memories 
on that particular processor, which structures do I need to consider?
So far, I am only flushing the i- and d-cache. I know there is a 
store-buffer somewhere, a directory for the cache, and I guess there is 
a TLB also, but I cannot find the structure name for it. By the way, 
what does TBE stand for?
Are there any other structures I have forgotten?

Thanks for your help.

/Mladen

Mike Marty wrote:
> If you execute your ruby0.flush-cache command when there is any 
> outstanding request in Ruby, then I can see why you would get this error.
> For instance consider if a cache controller is in state IS after issuing 
> a request to memory and then you interrupt the simulator and execute 
> that command.  There is still a TBE allocated in the cache controller 
> that says you are in state IS.  When the data comes back 100+ cycles 
> later after you flush the caches and start simulating again, it will try 
> to write the data to a cache tag that doesn't exist.
> --Mike
>
>
> Mladen Nikitovic wrote:
>   
> > Hi,
> >
> > I tried to implement a flushing mechanism for the caches by adding the 
> > following method to the CacheMemory class.
> >
> > template<class ENTRY>
> > inline
> > void CacheMemory<ENTRY>::Flush(void)
> >
> > {
> >   for (int i = 0; i < m_cache_num_sets; i++) {
> >     for (int j = 0; j < m_cache_assoc; j++) {
> >       m_cache[i][j].m_Address.setAddress(0);
> >       m_cache[i][j].m_LastRef = 0;
> >       m_cache[i][j].m_Permission = AccessPermission_NotPresent;
> >       m_cache[i][j].m_CacheState = L1Cache_State_L1_I;
> >     }
> >   }
> > }
> >
> > Now, in Chip.C I do the actual flushing:
> >
> > void Chip::flushCache(int id)
> > {
> >   m_L1Cache_L1IcacheMemory_vec[id]->Flush();
> >   m_L1Cache_L1DcacheMemory_vec[id]->Flush();
> > }
> >
> >
> > If I only flush the L1 I-cache it seem to work, but when I do it 
> > together with the L1 D-cache the simulator crashes.
> > simics> ruby0.flush-cache cpuNumber = 0
> > simics> c
> > failed assertion 'loc != -1' at fn ENTRY& 
> > CacheMemory<ENTRY>::lookup(const Address&) [with ENTRY = L1Cache_Entry] 
> > in system/CacheMemory.h:489
> > failed assertion 'loc != -1' at fn ENTRY& 
> > CacheMemory<ENTRY>::lookup(const Address&) [with ENTRY = L1Cache_Entry] 
> > in system/CacheMemory.h:489
> > At this point you might want to attach a debug to the running and get to the
> > crash site; otherwise press enter to continue
> > PID: 22541
> > Warning: Interrupt key pressed more than once.
> >          Pressing it again will force Simics back to the command prompt.
> >          This may corrupt the running simulation.
> >          Try waiting for Simics to stop first.
> >
> > Does anyone have an idea on what the problem might be? Has anyone tried 
> > to flush the caches before?
> > Regards,
> > Mladen
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