Re: [Gems-users] about a 64-core CMP system

[Guoqiang Yang <nkyangguoqiang@xxxxxxxxx>]

Hi there,

I constructed a 64-core CMP system using mesh topology (but 
FILE_SPECIFIED), with four directories connected to the four corners of 
the mesh. But when I tried to run a simulation in this system, I ran 
into error which was mentioned in my last email. After a one-after 
debugging, I finally found where things went wrong.
I put the following line in my trace file "36 0x2c49ac0 0 LD" for 
debugging.This line basically said core 36 want to load data in address 
"0x2c49ac0". And after the address mapping, the L1 Cache controller 
decided to access L2 Cache with "m_version = 4". So it issues GETS to 
that L2 Cache Controller, but surprisingly L2 Cache Controller with 
"m_version = 36" wakes up and tries to process that request. And when 
the L2 cache controller tries to add the requester into sharer list, it 
figures out that it should process this data, and reports the runtime 
error given  in my last email. To be precisely, error happens in file 
L2Cache_addSharer.C line 15.
Could anyone tell me why this would happen?

Many thanks,

Guoqiang Yang
=============================
Hi there,

I tried to construct a CMP system with 64 cores, using the way that 
Bruno mentioned several days ago. But I finally ran into the following 
error:
Runtime Error at ../protocols/MSI_MOSI_CMP_directory-L2cache.sm:275, 
Ruby Time: 15: assert failure,
I checked the source code and found that it failed in 
L2Cache_addSharer.C, where it tries to make sure that 
"map_L1CacheMachId_to_L2Cache(param_addr, param_requestor)) == 
m_machineID". So, I guess there is something wrong with the L2 mapping 
or the address mapping for 64-core system.
Does anyone know sth. about this? Any suggestion is appreciated.

Guoqiang Yang