Re: [Gems-users] Question about how OPAL handles DTLB miss

[Dan Gibson <degibson@xxxxxxxx>]

I'm afraid I'm not an opal expert. You should verify that your fastfowardSimics() function works as you expect it to, then check to see how the DTLB miss profiling works, but other than those, I have no further suggestions.

I will say that I implemented similar functionality in another simulator using more-or-less the same approach as your code below.

Regards,
Dan

On Tue, Apr 20, 2010 at 10:39 AM, shanshuchang <shanshuchang@xxxxxxxxx> wrote:

Thanks for your quick reply, Dan.

In some special situation, such as the instruction sequence is equal to a specified number, I would like to bypass the DTLB miss.

That is to say, when the Execute() function comes across a DTLB MISS for such a MEM inst, the OPAL module just appears to have a ideal DTLB.

I have found that there seems to be some codes considering the Ideal TLB like this:

 

if (TLB_IS_IDEAL &&

                  ((traptype == Trap_Fast_Instruction_Access_MMU_Miss) ||

                   (traptype == Trap_Fast_Data_Access_MMU_Miss))) {

                // fastforward through this trap

                fastforwardSimics(proc);

                // squash the pipeline

                partialSquash(m_iwin[proc].getLastRetired(), m_inorder_at[proc], op, proc, false);

                d->Squash();

                squash_pipeline = true;

                must_update_all = true;

              }

 

But after remake and run for some steps, the results indicate that the DTLB MISS handler was also involved by OPAL module.

I am not sure whether the above codes would cause the OPAL module to involve DTLB miss handler like takeTrap() function does?

 

Meanwhile, is there any advice on how to implement the Ideal DTLB?

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