[Gems-users] Only one processor executing instructions in Opal

[Bharat Singh <bharatsingh430@xxxxxxxxx>]

Hi,
I am trying to run splash-2 on a solaris 9 with MOSI_MSI_CMP_directory protocol. After initializing ruby and opal, if I type c then all the values printed by ruby0.dump-short-stats are 0. However instead of this if I do opal0.sim-start "temp1.output" opal0.sim-step 100000 opal0.stats, then I can see some results, but everything seems to be running on the first core. I am setting number of processors to 4, in the rubyconfig.default file. I am writing what is being shown by ruby0.dump-short-stats. Any suggestions will be very valuable. 


This is my simics script

read-configuration cholesky-started.config
istc-disable
dstc-disable
magic-break-enable
instruction-fetch-mode instruction-fetch-trace
cpu-switch-time 1
load-module ruby

load-module opal
ruby0.init
opal0.init
opal0.sim-start "temp1.output"
opal0.sim-step 100000
opal0.stats
ruby0.dump-short-stats

This is my Ruby dump.

Ruby_current_time: 240597
Ruby_start_time: 1
Ruby_cycles: 240596

Total_misses: 325
total_misses: 325 [ 325 0 0 0 ]
user_misses: 325 [ 325 0 0 0 ]
supervisor_misses: 0 [ 0 0 0 0 ]

instruction_executed: 100008 [ 100002 2 2 2 ]
simics_cycles_executed: 8 [ 2 2 2 2 ]

cycles_per_instruction: 9.62307 [ 2.40591 120298 120298 120298 ]
misses_per_thousand_instructions: 3.24974 [ 3.24994 0 0 0 ]

transactions_started: 0 [ 0 0 0 0 ]
transactions_ended: 0 [ 0 0 0 0 ]
instructions_per_transaction: 0 [ 0 0 0 0 ]

cycles_per_transaction: 0 [ 0 0 0 0 ]
misses_per_transaction: 0 [ 0 0 0 0 ]

L1D_cache cache stats: 
  L1D_cache_total_misses: 306
  L1D_cache_total_demand_misses: 190
  L1D_cache_total_prefetches: 116

  L1D_cache_total_sw_prefetches: 116
  L1D_cache_total_hw_prefetches: 0
  L1D_cache_misses_per_transaction: 306
  L1D_cache_misses_per_instruction: 0.00305985
  L1D_cache_instructions_per_misses: 326.814


  L1D_cache_request_type_LD:   61.7647%
  L1D_cache_request_type_ST:   38.2353%

  L1D_cache_access_mode_type_UserMode:   306    100%
  L1D_cache_request_size: [binsize: log2 max: 64 count: 306 average:    64 | standard deviation: 0 | 0 0 0 0 0 0 0 306 ]

L1I_cache cache stats: 
  L1I_cache_total_misses: 19
  L1I_cache_total_demand_misses: 19
  L1I_cache_total_prefetches: 0
  L1I_cache_total_sw_prefetches: 0
  L1I_cache_total_hw_prefetches: 0
  L1I_cache_misses_per_transaction: 19

  L1I_cache_misses_per_instruction: 0.000189991
  L1I_cache_instructions_per_misses: 5263.42

  L1I_cache_request_type_IFETCH:   100%

  L1I_cache_access_mode_type_UserMode:   19    100%
  L1I_cache_request_size: [binsize: log2 max: 64 count: 19 average:    64 | standard deviation: 0 | 0 0 0 0 0 0 0 19 ]

L2_cache cache stats: 
  L2_cache_total_misses: 325
  L2_cache_total_demand_misses: 209
  L2_cache_total_prefetches: 116
  L2_cache_total_sw_prefetches: 116
  L2_cache_total_hw_prefetches: 0
  L2_cache_misses_per_transaction: 325

  L2_cache_misses_per_instruction: 0.00324984
  L2_cache_instructions_per_misses: 307.708

  L2_cache_request_type_GETS:   58.1538%
  L2_cache_request_type_GET_INSTR:   5.84615%
  L2_cache_request_type_GETX:   3.07692%

  L2_cache_request_type_UPGRADE:   32.9231%

  L2_cache_access_mode_type_UserMode:   325    100%
  L2_cache_request_size: [binsize: log2 max: 8 count: 325 average:     8 | standard deviation: 0 | 0 0 0 0 325 ]

-- 
Bharat Singh
3rd Year Comp. Sci and Engg.
IIT Madras