[Gems-users] (no subject)

[Artur Podobas <apodobas@xxxxxxxxx>]

So Im currently trying out some configurations using 
MS_MOSI_CMP_directory and I have a question regarding the I-fetches. I 
have disabled FAST_PATH in the ruby config. The architecture that Im 
using under RUBY is Sparc (not Opal but normal Simics Sparc).

As I understand it, on each instruction fetch the cache-controller 
should receive a I-fetch request. Did is however not the case. Here's an
 example ruby-dump-stat that shows that there are extremly few ifetches 
being issued:

Also the amount of I-fetches (see below) seems to be the exact same 
number as Duplicate instruction fetches. Am I doing/thinking wrongly 
here?

 --- L1Cache ---
 - Event Counts -
Load  136234
Ifetch  560
Store  98589
L1_INV  0
L1_INV_S  0
L1_DownGrade  0
L1_Data  6538
L1_Data_S  0
L1_Data_I  0
L1_PutAck  4555
L1_Replacement  4555
L1_WriteBack  0

 - Transitions -
NP  Load  2046
NP  Ifetch  560

NP  Store  3524
NP  L1_Replacement  0 <-- 
NP  L1_WriteBack  0 <-- 

L1_I  Load  0 <-- 
L1_I  Ifetch  0 <-- 
L1_I  Store  0 <-- 
L1_I  L1_Replacement  0 <-- 
L1_I  L1_WriteBack  0 <-- 

L1_S  Load  35209
L1_S  Ifetch  0 <-- 
L1_S  Store  408
L1_S  L1_INV_S  0 <-- 
L1_S  L1_Replacement  1304
L1_S  L1_WriteBack  0 <-- 

L1_M  Load  98979
L1_M  Ifetch  0 <-- 
L1_M  Store  94657

L1_M  L1_INV  0 <-- 
L1_M  L1_DownGrade  0 <-- 
L1_M  L1_Replacement  3251
L1_M  L1_WriteBack  0 <-- 

L1_IS  L1_INV_S  0 <-- 
L1_IS  L1_Data  2606
L1_IS  L1_Data_I  0 <-- 

L1_ISI  L1_Data  0 <-- 

L1_IM  L1_INV  0 <-- 
L1_IM  L1_INV_S  0 <-- 
L1_IM  L1_DownGrade  0 <-- 
L1_IM  L1_Data  3932
L1_IM  L1_Data_S  0 <-- 
L1_IM  L1_Data_I  0 <-- 

L1_IMI  L1_Data  0 <-- 

L1_IMS  L1_INV_S  0 <-- 
L1_IMS  L1_Data  0 <-- 

L1_IMSI  L1_Data  0 <-- 

L1_SI  L1_INV_S  0 <-- 
L1_SI  L1_PutAck  1304

L1_MI  L1_INV  0 <-- 
L1_MI  L1_DownGrade  0 <-- 
L1_MI  L1_PutAck  3251


thanks and Best regards