Re: [Gems-users] Some problems on the trace of MESI_CMP_filter_Directory protocol(fully)

[Marc Lupon <mlupon@xxxxxxxxxx>]

Hi Ruzhu,

When an L1-cache needs to read/write a data that it is in I or NP, it 
has to be sure that no other core has modified it inside a transaction. 
So, the L1-cache asks the directory who has that line. If the data is 
not present in the L2 cache (NP), the directory does not know if this 
data belongs to any in-flight transaction (maybe the transaction 
overflowed the L2-cache), and broadcast the requests to all the other 
cores.
Remote cores check for conflict in their signatures 
(L1CacheCheck_Read_Write_Filter) and reply to the requester, whom 
gathers the acknowledgements (or nacks if there is a conflict). After 
collecting all the responses, the reader/writer is able to acquire the 
exclusiveness of the line (MT state in the L2-cache).
Regards,

Marc


Hi all:
   I am sorry to sent the incomplete mail by my misoperation some minutes ago.
I want to understand the mechanism in MESI_CMP_filter_Directory 
protocol, I used tester.exec to replay the simple trace like wiki in 
WISC.
The trace file only contains these instructions below:
  7  0x400 0 LD
  1  0x400 0 LD
  8  0x400 0 LD
12  0x400 0 ST
  1  0x400 0 LD

Then  I use a 4*4 mesh topology for interconnect and adding some 
configurations in tester.defaults to make it support XACT.
This is partial output from stats file.

      1   7  -1        Seq               Begin       >       [0x400, 
line 0x400] LD
      2   0   7    L1Cache                Load     NP>IS     [0x400, 
line 0x400]  request: Timestamp: 0 PA: [0x400, line 0x400] Type: LD 
VPC: [0x0, line 0x0] Mode: UserMode PF: Yes VA: [0x0, line 0x0] Thread: 
0 Exposed: 00
      9   0   0    L2Cache             L1_GETS     NP>ISS    [0x400, 
line 0x400]  request: Timestamp: 0 Requestor: L1Cache-7 Dest: [NetDest 
(3) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  
- 0 0 0 0  - ] PA: [0x400, line 0x400] Type: GETS Mode: UserMode PF: 
Yes requestor: L1Cache-7 [0x400, line 0x400]
     17   0   0    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     20   0   1    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     23   0  15    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     23   0   3    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     23   0   6    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     23   0   8    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     23   0   2    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     25   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: 0 [0x400, line 0x400] 1 after 
pendingAcks: -1 sender: L1Cache-0
     26   0   5    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     26   0  14    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     26   0   4    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     26   0   9    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     29   0  11    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     29   0  10    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     29   0  12    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     29   0  13    L1CacheCheck_Read_Write_Filter     NP>NP     
[0x400, line 0x400]  [0x400, line 0x400]
     31   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -1 [0x400, line 0x400] 1 after 
pendingAcks: -2 sender: L1Cache-6
     31   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -2 [0x400, line 0x400] 1 after 
pendingAcks: -3 sender: L1Cache-1
     31   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -3 [0x400, line 0x400] 1 after 
pendingAcks: -4 sender: L1Cache-8
     34   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -4 [0x400, line 0x400] 1 after 
pendingAcks: -5 sender: L1Cache-15
     37   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -5 [0x400, line 0x400] 1 after 
pendingAcks: -6 sender: L1Cache-9
     37   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -6 [0x400, line 0x400] 1 after 
pendingAcks: -7 sender: L1Cache-3
     37   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -7 [0x400, line 0x400] 1 after 
pendingAcks: -8 sender: L1Cache-2
     37   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -8 [0x400, line 0x400] 1 after 
pendingAcks: -9 sender: L1Cache-5
     40   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -9 [0x400, line 0x400] 1 after 
pendingAcks: -10 sender: L1Cache-4
     40   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -10 [0x400, line 0x400] 1 after 
pendingAcks: -11 sender: L1Cache-14
     43   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -11 [0x400, line 0x400] 1 after 
pendingAcks: -12 sender: L1Cache-10
     46   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -12 [0x400, line 0x400] 1 after 
pendingAcks: -13 sender: L1Cache-13
     46   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -13 [0x400, line 0x400] 1 after 
pendingAcks: -14 sender: L1Cache-11
     46   0   7    L1Cache                 Ack     IS>IS     [0x400, 
line 0x400]  before pendingAcks: -14 [0x400, line 0x400] 1 after 
pendingAcks: -15 sender: L1Cache-12
     53   0   0  Directory               Fetch      I>I      [0x400, 
line 0x400]
    210   0   0    L2Cache            Mem_Data    ISS>ISS_MB [0x400, 
line 0x400]
    230   0   7    L1Cache   L2_Exclusive_Data     IS>IS_E   [0x400, 
line 0x400]  before pendingAcks: -15 [0x400, line 0x400] -15 after 
pendingAcks: 0 sender: L2Cache-0 Triggering All_Acks
    231   7  -1        Seq                Done       >       [0x400, 
line 0x400] 230 cycles NULL LD Yes
    231   0   7    L1Cache             Ack_all   IS_E>E      [0x400, 
line 0x400]
    237   0   0    L2Cache   Exclusive_Unblock ISS_MB>MT     [0x400, 
line 0x400]
    301   1  -1        Seq               Begin       >       [0x400, 
line 0x400] LD
    302   0   1    L1Cache                Load     NP>IS     [0x400, 
line 0x400]  request: Timestamp: 0 PA: [0x400, line 0x400] Type: LD 
VPC: [0x0, line 0x0] Mode: UserMode PF: Yes VA: [0x0, line 0x0] Thread: 
0 Exposed: 00
    309   0   0    L2Cache             L1_GETS     MT>MT_IIB [0x400, 
line 0x400]  request: Timestamp: 0 Requestor: L1Cache-1 Dest: [NetDest 
(3) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  
- 0 0 0 0  - ] PA: [0x400, line 0x400] Type: GETS Mode: UserMode PF: 
Yes requestor: L1Cache-1 [0x400, line 0x400]
    320   0   7    L1Cache            Fwd_GETS      E>S      [0x400, 
line 0x400]
    328   0   0    L2Cache       WB_Data_clean MT_IIB>MT_SB  [0x400, 
line 0x400]
    331   1  -1        Seq                Done       >       [0x400, 
line 0x400] 30 cycles NULL LD Yes
My question is why the first LD 0x400 on Processor 7 need to run 
L1CacheCheck_Read_Write_Filter  on other processors. After the first LD 
on Processor 7 L2Cache transform from ISS_MB to MT, which indicates "L2 
cache entry Modified in a local L1, assume L2 copy stale" It make me 
very puzzle, I used to think LD just need to run 
L1CacheCheck_Write_Filter and L2 cache should be in SS.
Can anybody explain it why does it happened?

Another problem is when I look through the protocol file, I find a 
problem on access permission in *L1cache.sm which *E* state is set to 
be read-only. *E* state in MESI protocol should be Read-writable, and I 
do not know the reason changing it here.
I am looking forward to heard any explanations on these problems. 
Thanks in advance.

Sincerely yours:
Ruzhu