Date: | Sat, 13 Aug 2011 17:31:54 +0430 |
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From: | Hamid Reza Khaleghzadeh <khaleghzadeh@xxxxxxxxx> |
Subject: | [Gems-users] disable Cache to cache connection in Gems |
Hi I have simulated a quad-core processor by Gems that contains two L2 caches and each L2 is shared by two cores and coherency protocol is MOESI-CMP-directory. I found that when a data misses in one of the L2 caches and this data exists in another L2, the data is read via L2 cache_to_L2 cache instead of memory. I intend to modify Gems where when a miss occurs in L2, data is read from memory. Could you tell me how i can do it? Thanks for you answer in advance. |
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