Re: [Gems-users] Cache to Cache transfer

[Greg Byrd <gbyrd@xxxxxxxx>]

I just want to point out one consequence of the approach that Byn 
suggests.  If you have a separate network port for these messages, then 
you must (I believe) have a separate virtual network for that type of 
message, so that it gets delivered to the correct port.  Messages on 
that VN will proceed independently of messages on the other VNs.  So if 
the ordering of this message, with respect to other request or response 
messages, is important, then you might need to modify the approach.
...Greg


On 1/3/11 4:48 PM, Byn Choi wrote:
> Hi Bharat-
>
> I've only worked with MESI_SCMP_bankdirectory protocol my following 
> comments may not be too relevant, but I'm hoping it'll be of use.
> The only type of cache-to-cache transfer that happens in a stock 
> version of the protocol is the "response" portion of a 3-hop miss, 
> i.e. L1cache#0 --request--> L2(directory) --redirected-> L1cache#1 
> --response--> L1cache#0. I have implemented a cache-to-cache transfer 
> that proactively sends a line from one cache to another, i.e. as a 
> "request."
> From what I can deduce, I think what you are trying to do is somewhat 
> similar, at least at the low-level. Whatever the trigger, once 
> determined that you want to "spill" this line, you are requesting this 
> line be transferred to the other cache, i.e. the other cache isn't 
> expecting this as a response of something it had requested prior.
> The stock implementation didn't have anything for this, so I had to 
> add some manual changes. Aside from adding new message types, etc, to 
> recognize such transaction, one crucial thing to do was to add an 
> in_port() on the receiving side. The network is setup to deliver 
> messages anywhere as long as the messages are addressed correctly, but 
> the receiver must be listening on that channel. Again, this wasn't 
> setup before because the protocol didn't have any direct 
> cache-to-cache transfers for "request" messages.
> Btw, I maybe wrong, but that bit sounds somewhat like the "F" of the 
> Intel MESIF protocol.
> Thanks,
>
> Byn
>
> On Jan 3, 2011, at 12:20 PM, Bharat Singh wrote:
>
> > Hi everyone,
> >
> > I am using MSI_MOSI_CMP_directory protocol with 4 processors on a 
> > single chip.
> > I am trying to modify the cache replacement policy, and I want to 
> > spill cache entries. So for that I want to transfer data between 2 
> > processors. I have no problems if this has to be done randomly 
> > between processors. I want to transfer a cache block to another cache 
> > depending on a bit which I am getting in CacheProbe function in 
> > CacheMemory.h. So if that bit is set I will update the bit and 
> > transfer the cache block to another cache else I will evict the 
> > block. I want to know is there a function or a set of functions in 
> > Ruby which help us in implementing Cache to Cache transfers. Its not 
> > been a long time since I have been using Ruby so excuse me for my 
> > ignorance. Any information regarding the above problem will be very 
> > useful. Thanks in advance.
> > --
> > Bharat Singh
> > 3rd Year Comp. Sci and Engg.
> > IIT Madras
> > _______________________________________________
> > Gems-users mailing list
> > Gems-users@xxxxxxxxxxx
> > https://lists.cs.wisc.edu/mailman/listinfo/gems-users
> > Use Google to search the GEMS Users mailing list by adding 
> > "site:https://lists.cs.wisc.edu/archive/gems-users/"; to your search.
> ---
> Byn Choi
> Ph.D. Candidate in Computer Science
> University of Illinois, Urbana-Champaign
>
> _______________________________________________
> Gems-users mailing list
> Gems-users@xxxxxxxxxxx
> https://lists.cs.wisc.edu/mailman/listinfo/gems-users
> Use Google to search the GEMS Users mailing list by adding 
> "site:https://lists.cs.wisc.edu/archive/gems-users/"; to your search.