Re: [Gems-users] How doest GEMS simulate traps?

[Gedare Bloom <gedare@xxxxxxxxxxxxxx>]

The following is my understanding, and may not be 100% accurate.

All traps are caused by Simics. Opal models and executes some traps,
for example the register window traps, which happen quite often so it
is important to have decent performance. If Opal does not model a
particular trap, then when the state check occurs and fails, the
pipeline is flushed and Opal starts to fetch from the new
Simics-provided pc. That is why some traps are modelled by Opal,
especially the regwin traps which can be accurately predicted. In
cases Opal doesn't model the trap, it sets some appropriate flag to
use the functional simulator for the trap execution. However, due to
OoO / Speculation, even some of the modelled traps may be exected by
Opal but not be executed by Simics.  Still, this should only result in
the flushing of the pipeline and some wasted cycles, since Opal does
not commit any architected state changes until after the state check
with Simics. You can see the difference somewhere in the Opal stats,
it shows which traps happen in Opal and which in Simics.

So I guess the short answer is that some traps that are modelled in
Opal are executed by GEMS, but that is not the set of all traps. If
Opal models a trap, it will run the trap handler independently of
Simics and will check later if that was correct. If the trap handler
should not have been run, those instructions are squashed, but they
did get simulated.

-Gedare

2011/3/21 Philip Garcia <pcgarcia@xxxxxxxx>:
> I don't see why traps wouldn't be handled by the functional simulator
> simics.  I know code for TLB misses runs regularly in the OS, and that is
> just a trap.  It's possible some traps aren't implemented in simics, but I
> don't really know which ones those are.  If the traps are required for
> proper functional operation of the CPU (such as for TLB misses), simics must
> handle them.  I know opal has some trap handling cases inside of it, but I
> am not the most familiar with it.
> Phil
> On Mar 21, 2011, at 10:06 AM, Peter Fang wrote:
>
> As we know, some traps only happens in the timing simulator GEMS, and do not
> happen in the functional simulator Simics. When a trap happens, GEMS should
> fetch
> instructions from the trap_pc which represent trap handling instructions.
>
> However, in the GEMS implementation, a state check between GEMS and Simics
> is
> forced when each instruction is retired. And after the state check for the
> trap
> instruction, the pc will be set according to Simics, which is pc+4, not
> trap_pc. So
> those trap handling instructions are actually not simulated??
>
> 2011-03-21
> ________________________________
> Peter Fang
> ________________________________
> 发件人： Peter Fang
> 发送时间： 2010-10-13  16:36:42
> 收件人： gems-users
> 抄送：
> 主题： How does simics set its pc (program counter)?
> Hi, everyone!
> I got a strange problem for Simics 3.0.31.
> When I step simics one instruction per core for a sparc multi-core
> simulation,
> it never ends. And the strange thing is that for core0, after it executes an
> instruction cmp %o7, 0, %g0, the next pc is set to 0x105cde4. And no
> instruction
> in other cores modify the next pc of core0. However, when I step for core0
> again,
> the instruction is executed at pc 0x10009c0, surprisingly not the next pc
> value of
> last instruction!!!
> So I wonder how simics set its pc. Is it set to the next pc value of last
> instruction? Any idea?
>
> 2010-10-13
> ________________________________
> Peter Fang
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