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As we know, some traps only
happens in the timing simulator GEMS, and do not
happen in the functional simulator Simics. When a trap happens, GEMS
should fetch
instructions from the trap_pc which represent trap
handling instructions.
However, in the GEMS
implementation, a state check between GEMS and Simics is
forced when each
instruction is retired. And after the state check for the trap
instruction, the pc will be
set according to Simics, which is pc+4, not trap_pc.
So
those trap handling
instructions are actually not
simulated??
2011-03-21
Peter
Fang
发件人： Peter Fang
发送时间： 2010-10-13 16:36:42
收件人： gems-users
抄送：
主题： How does simics set its pc
(program counter)?
Hi, everyone!
I got a strange problem for
Simics 3.0.31.
When I step simics one
instruction per core for a sparc multi-core simulation,
it never ends. And the strange thing is that for core0,
after it executes an
instruction cmp %o7, 0, %g0, the
next pc is set to 0x105cde4. And no instruction
in other cores modify the next pc of core0. However,
when I step for core0 again,
the instruction is executed at pc 0x10009c0, surprisingly not the next pc value of
last instruction!!!
So I wonder how simics set its
pc. Is it set to the next pc value of last
instruction? Any idea?
2010-10-13
Peter
Fang
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