Re: [Gems-users] Bypass L1 cache?

[Venkatanathan Varadarajan <venkatv@xxxxxxxxxxx>]

The answer to your question depends more on what you are going to by pass (is it in the protocol level or just direct access to data present in L2)?

The memory subsystem simulated by ruby is very much tied to the slicc interface (starting from L1, the control is taken over by the slicc interface (the slicc generated code) from the system/Sequencer).

-Venkat
On 05/11/2011 11:07 AM, Binh Q. Pham wrote:

Hi,
In ruby/slicc_interface/AbstractChip.h, I saw the following declaration:
// pulic data structures
  Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L1DcacheMemory_vec;
  Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L1IcacheMemory_vec;
  Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_cacheMemory_vec;
  Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L2cacheMemory_vec;
  Vector < CacheMemory<L1Cache_Entry>* > m_L2Cache_L2cacheMemory_vec;

For the first two declarations, I guess they are L1 data cache and L1 instruction cache respectively. However, I don't understand the other three declarations. Does anyone know what is going on here?My goal is to bypass L1 cache for a certain request, and pass it directly to L2 cache. I am thinking I can call the function tryCacheAccess in ruby/system/Sequencer.C on a L2 cache object to do this. Am I on the right track here?

Thank you,
Binh

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-- 
Venkatanathan Varadarajan,
Graduate Student,
Department of Computer Sciences,
University of Wisconsin - Madison.
http://pages.cs.wisc.edu/~venkatv/