This is the 1st February 2007 Digest of SIGARCH Messages (sigarch-feb07a):
* CARD Call for Participation: Workshop on Computer Architecture Research Directions (with HPCA 2007)
http://www.ele.uri.edu/CARD
Submitted by Joshua Yi <jjyi@xxxxxxxxxxx>
* New papers published online by Computer Architecture Letters
http://www.comp-arch-letters.org
Submitted by Kevin Skadron <skadron@xxxxxxxxxxxxxxx>
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Associate Professor Phone: 512-471-9795
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Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* CARD Call for Participation: Workshop on Computer Architecture Research Directions (with HPCA 2007)
Call For Participation
The Workshop on Computer Architecture Research Directions
CARD 2007
http://www.ele.uri.edu/CARD
Held in conjunction with HPCA 2007
February 11, 2007
Phoenix, AZ
Introduction:
=============
Decreasing transistor feature sizes simultaneously offer increased opportunities
and challenges for computer architecture researcher and designers. With hundreds
of millions or billions of transistors, computer architects can propose complex
microarchitectural enhancements, increase processor functionality, or implement
multiple processors-per-chip. On the other hand, among other problems, shrinking
transistor widths also lead to increased static power dissipation; higher power
densities, which require active thermal management; and decreased reliability
(due to soft-errors and circuit degradation).
The future directions of such open research problems are unclear. The
traditional way to tackle open research problems is for experts in the field to
write papers and present those papers in conferences. After each presentation,
other experts may ask one or two detailed questions that are often too complex
and assume too much background knowledge for many audience members. After the
session, the experts may assemble to discuss finer points, reach some consensus
and then go off to their respective bases to do the next generation of research
to write the next paper.
While such a model is fine for the experts, it often is not very helpful to an
average audience member. Instead, a direct discussion between experts would be
far more useful. Such a discussion, properly moderated by another expert, could
quickly focus in on what are accepted results and parameters of the subject,
what are the open questions and areas of disagreement of the subject and what
are the most promising approaches to those open problems. Audience questions,
properly filtered by the moderator to ensure relevance, would further guide the
discussion.
Accordingly, the purpose of this workshop is to serve as a forum in which
experts in each field can debate the state of the field and future directions.
The format is designed to quickly focus on areas of disagreement, rather than
expounding on areas of agreement which, presumably, have ceased to be
controversial, at least between the two panelists.
The hope is that the workshop will be useful to a diverse audience from a
graduate student looking for good thesis topic areas to a senior researcher who
wants to hear the opinions of other area experts.
More specifically, this workshop consists of following four 60 minute
mini-panels:
Description of Panels:
======================
The panels are as follows:
Mini-panel #1: Single-threaded vs. Multi-threaded
Yale Patt (University of Texas) vs. Mark Hill (University of Wisconsin)
Moderator: Joel Emer (Intel)
Mini-panel #2: Reliability
Shubhendu Mukherjee (Intel) vs. Scott Mahlke (University of Michigan)
Moderator: Antonio Gonzalez (Intel and UPC-Barcelona)
Mini-panel #3: Low-Power Design and Temperature Management
Pradip Bose (IBM) vs. Kanad Ghose (SUNY-Binghamton)
Moderator: Kevin Skadron (University of Virginia)
Mini-panel #4: Security
Leendert Van Doorn (IBM) vs. Cetin Kaya Koc (Oregon State University)
Moderator: Jean-Pierre Seifert (University of Innsbruck)
The mini-panels are intended to help clarify the open issues of each topic and
to discuss those open issues. The hope is that the workshop will be useful to a
diverse audience from a graduate student looking for good thesis topic areas to
a senior researcher who wants to hear the opinions of other area experts.
Organizers:
===========
Derek Chiou, University of Texas
Resit Sendag, University of Rhode Island
Joshua J. Yi, Freescale Semiconductor
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* New papers published online by Computer Architecture Letters
Computer Architecture Letters announces our two most recent papers (we
didn't sent out an announcement over the winter holidays). They
are available now via IEEE Xplore. We continue to seek new
submissions and remain committed to fast and accurate review. Our mean
time to decision remains one month, with an acceptance rate of
approximately 22%. For more information on submission, please see
http://www.comp-arch-letters.org
- C. Blundell, E. C. Lewis, and M. M. K. Martin. "Subtleties of Transactional Memory Atomicity Semantics." Volume 5, Nov. 2006.
- G. Price and M. Vachharajani. "A Case for Compressing Traces with BDDs." Volume 5, Nov. 2006.
Abstracts
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- C. Blundell, E. C. Lewis, and M. M. K. Martin. "Subtleties of Transactional Memory Atomicity Semantics." Volume 5, Nov. 2006.
Abstract:
Transactional memory has great potential for simplifying multithreaded programming by allowing programmers to specify regions of the program that must appear to execute atomically. Transactional memory implementations then optimistically execute these transactions concurrently to obtain high performance. This work shows that the same atomic guarantees that give transactions their power also have unexpected and potentially serious negative effects on programs that were written assuming narrower scopes of atomicity. We make four contributions: (1) we show that a direct translation of lock-based critical sections into transactions can introduce deadlock into otherwise correct programs, (2) we introduce the terms strong atomicity and weak atomicity to describe the interaction of transactional and non-transactional code, (3) we show that code that is correct under weak atomicity can deadlock under strong atomicity, and (4) we demonstrate that sequentially composing transactional !
code can also introduce deadlocks. These observations invalidate the intuition that transactions are strictly safer than lock-based critical sections, that strong atomicity is strictly safer than weak atomicity, and that transactions are always composable.
- G. Price and M. Vachharajani. "A Case for Compressing Traces with BDDs ." Volume 5, Nov. 2006.
Abstract:
Instruction-level traces are widely used for program and hardware analysis. However, program traces for just a few seconds of execution are enormous, up to several terabytes in size, uncompressed. Specialized compression can shrink traces to a few gigabytes, but trace analyzers typically stream the the decompressed trace through the analysis engine. Thus, the complexity of analysis depends on the decompressed trace size (even though the decompressed trace is never stored to disk). This makes many global or interactive analyses infeasible. This paper presents a method to compress program traces using binary decision diagrams (BDDs). BDDs intrinsically support operations common to many desirable program analyses and these analyses operate directly on the BDD. Thus, they are often polynomial in the size of the compressed representation. The paper presents mechanisms to represent a variety of trace data using BDDs and shows that BDDs can store, in 1~GB of RAM, the entire data-de!
pendence graph of traces with over 1 billion instructions. This allows rapid computation of global analyses such as heap-object liveness and dynamic slicing.
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