This is the 1st November 2007 Digest of SIGARCH Messages (sigarch-nov07a):
* Solicitaion for Proposals: NSF Computing Processes and Artifacts (CPA) cluster
http://nsf.gov/pubs/2007/nsf07587/nsf07587.htm
Submitted by Timothy M. Pinkston <tpink@xxxxxxx>
* NSF "Expeditions in Computing" (Expeditions) Solicitation
http://nsf.gov/pubs/2007/nsf07592/nsf07592.htm
Submitted by Timothy M. Pinkston <tpink@xxxxxxx>
* General Execution-driven Multiprocessor Simulator (GEMS) Release 2.0
http://www.cs.wisc.edu/gems/
Submitted by Mark D. Hill <markhill@xxxxxxxxxxx>
* HIPS 2008 Call for Papers: 13th International Workshop on High-Level Parallel
Programming Models and Supportive Environments
http://cobweb.ecn.purdue.edu/~smidkiff/hips/
Submitted by Sam Midkiff <smidkiff@xxxxxxxxxx>
* New papers published online by IEEE Computer Architecture Letters
http://www.comp-arch-letters.org
Kevin Skadron <skadron@xxxxxxxxxxxxxxx>
* SMART'08 Call for Papers: 2nd Workshop on Statistical and Machine learning approaches
to ARchitecture and compilaTion
http://www.hipeac.net/smart-workshop.html
Submitted by Grigori Fursin <grigori.fursin@xxxxxxxx>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx
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Doug Burger Office: 3.432 ACES
Associate Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* Solicitaion for Proposals: NSF Computing Processes and Artifacts (CPA) cluster
The new solicitation for architecture proposals to the NSF Computing
Processes and Artifacts (CPA) cluster is up and available at
http://nsf.gov/pubs/2007/nsf07587/nsf07587.htm. The proposal deadline is
December 7, 2007. There are some changes compared to last year's
solicitation, so submitters should carefully read the new solicitation. One
notable change is that an investigator may participate on at most two
proposals (instead of just one) as long as at least one of the proposals is
a "team" or "major team" proposal, but only a few proposals in these
categories are expected to be awarded overall.
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* NSF "Expeditions in Computing" (Expeditions) Solicitation
A new NSF CISE program called "Expeditions in Computing" (Expeditions)
provides the opportunity for the computing research community to pursue
ambitious, compelling, and transformative research agendas that promise
disruptive innovations in the computing and information fields. Funded at
levels up to $2,000,000 per year for five years, awarded projects are
expected to explore far-reaching research and education activities motivated
by hard problems and/or compelling applications. Teams of investigators
from within or across departments or institutions are encouraged to combine
their expertise and talents to forge well-integrated research appropriate
for the Expeditions program. More information about Expeditions is
available at http://nsf.gov/pubs/2007/nsf07592/nsf07592.htm. Note the
following deadlines: a Letter of Intent is due November 5, 2007, and the
Preliminary Proposal is due December 30, 2007. It is estimated that only 20
collaborating teams will be invited to submit a full proposal due on April
1, 2008, with only 3 of those proposals anticipated for award.
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* General Execution-driven Multiprocessor Simulator (GEMS) Release 2.0
http://www.cs.wisc.edu/gems/
In 2005, the Wisconsin Multifacet Project released our General Execution-driven Multiprocessor
Simulator (GEMS). GEMS is a set of modules for Virtutech Simics that enables detailed
simulation of multiprocessor systems, including Chip-Multiprocessors (CMPs). Already,
GEMS has been downloaded by over 750 users and been used in 19 papers from outside Wisconsin
(http://www.cs.wisc.edu/gems/publications.html).
In October 2007, the GEMS team has put its finishing touches on the new 2.0 release, and it
is now available for download at:
http://www.cs.wisc.edu/gems/download.html
Notable features of this release include:
(1) Non-LogTM specific features/updates:
- x86 support for Ruby (Thanks Soohong Kim for the patch)
- Simultaneous multi-threading (SMT) support in Opal
- Protocol fixes
- Bash scripts to automate generation of "naked/OS/whatever"
checkpoints*
(2) LogTM-specific features/updates:
- single-chip transactional CMP directory protocol, with sticky-M & sticky-S directory
states
- support for partial rollback, closed and open nesting
- support for compensating and commit actions through our software handler
- "Perfect" Signature support (can emulate infinite RW bits) and Finite Signature support
(Bit-Select & H3)
- Summary signature support (Perfect & finite)
- Limited LogTM-SE virtualization support, all in simulator**
- support for ISCA '07 Pathologies systems:
Eager conflict detection, Lazy version management
Lazy conflict detection, Lazy version management
Eager conflict detection, Eager version management, with & without store-set
prediction
Hybrid conflict resolution policy
- Sample transactional micro-benchmarks
Please note that the prior SMP LogTM protocol using RW bits is no
longer supported in this release. Finite RW bit (LogTM-like)
functionality can be emulated by using "Perfect" signatures & the released CMP protocol.
(3) Future plans include enhanced interconnection network support from Li-Shiuan Peh's
groups at Princeton University.
Footnotes:
* = Full support for building apache, zeus, and jbb workload
checkpoints should be expected in a patch released shortly.
** = We plan on integrating more stable support with OpenSolaris in the
future.
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* HIPS 2008 Call for Papers: 13th International Workshop on High-Level Parallel
Programming Models and Supportive Environments
13th International Workshop on High-Level Parallel Programming Models and Supportive
Environments
held in conjunction with IPDPS 2008
April 14th, 2008, Hyatt Regency Resort in Miami, Florida
Scope:
The 13th HIPS workshop is a full-day meeting to be held at the IPDPS 2007 focusing on
high-level programming of chip multi-processors (multi-core PCs), computing clusters,
and massively-parallel machines. Like its predecessors, the workshop seeks cross-fertilizing
research in areas of parallel applications, language design, compilers, run-time systems, and
programming tools. It provides a timely and interactive forum for scientists and engineers to
present the latest ideas, findings, and tools in these rapidly changing fields. This year we
especially encourage innovative approaches for programming the increasingly popular chip
multi-processors and the fast growing large-scale parallel systems. The topics of interest
include but are not limited to
* New programming constructs and languages for exploiting parallelism and locality
* Experience with and improvements for existing parallel languages and run-time
environments such as MPI, OpenMP, HPF, Cilk, UPC, and Co-array Fortran.
* Parallel programming tools and environments
* Scalable tools infrastructures
* Scalable performance analysis, modeling, and monitoring
* OS and architectural support for parallel programming
* Scalable debugging
* Software and system support for extreme scalability
* Software and system support for fault tolerance
* Issues related to NUMA in multicores
Schedule and Submission Procedure:
Papers due: November 27th, 2007
Author notification: January 7th, 2008
Camera-ready final papers due (tentative date): January 28th, 2008 (strict deadline
set by the IPDPS conference)
HIPS workshop: Monday, April 14th, 2008
The HIPS workshop proceedings will be published electronically along with the IPDPS
conference proceedings. Submitted manuscripts should be formatted according to IPDPS
proceedings guidelines: 10-point fonts, single-spaced, and two-column format. The page
size is US letter (8.5x11 inch). The maximal length is 8 pages. All papers must be in
English.
The workshop uses EDAS conference manager for submission and notification. An author needs
to register with EDAS as a user if this has not been done previously. Start the paper by
providing the title and the abstract in plain text, and then submit the full paper in pdf.
Please click here to start the process and follow the instructions.
Committees:
Workshop Co-chairs
Martin Schulz Lawrence Livermore National Lab
Sam Midkiff Purdue University
Steering Committee
Rudolf Eigenmann Purdue University, USA
Michael Gerndt Technische Universität München, Germany
Frank Müller North Carolina State University, USA
Craig Rasmussen Los Alamos National Laboratory, USA
Martin Schulz Lawrence Livermore National Laboratory, USA
Program Committee
Gabriel Antoniu IRISA-INRIA, France
Bronis R. de Supinski Lawrence Livermore National Laboratory, CA, USA
Franz Franchetti Carnegie Mellon University, PA, USA
Michael Gerndt Technische Universität München, Germany
Karen Karavanic Portland State University, OR, USA
Hironori Kasahara Waseda University, Japan
Dieter Kranzlmüller Johannes Kepler University, Austria
David Lowenthal University of Georgia, GA, USA
Bernd Mohr Jülich Supercomputer Center, Germany
Jose Moreira IBM T.J. Watson Research Center, NY, USA
Vijay Pai Purdue University, IN, USA
Craig Rasmussen Los Alamos National Laboratory, NM, USA
Alexander Reinefeld Zuse Institute, Germany
Philip C. Roth Oak Ridge National Laboratory, TN, USA
Saday Sadayappan Ohio State University, OH, USA
David Sehr Google, CA, USA
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* New papers published online by IEEE Computer Architecture Letters
Computer Architecture Letters announces our two most recent papers, which are available now
via IEEE Xplore (see "Forthcoming" articles) or the IEEE Computer Society Digital Library.
We happy to report that, as recognition of Computer Architecture Letters has grown, the
submission rate is up nearly 70% over the same time last year. We continue to seek new
submissions and remain committed to fast and accurate review. Our mean time to decision in
2007 has been 25 days, with an acceptance rate of approximately 24%. For more information
on submission, please see http://www.comp-arch-letters.org
- G. Yalcun and O. Ergin. "Using Tag-Match Comparators for Detecting Soft Errors. Computer
Architecture Letters, vol. 6, Oct. 2007.
- A. Roth. "Physical Register Reference Counting." Computer Architecture Letters, vol. 6,
Oct. 2007.
Abstracts
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- G. Yalcun and O. Ergin. "Using Tag-Match Comparators for Detecting Soft Errors. Computer
Architecture Letters, vol. 6, Oct. 2007.
Abstract:
Soft errors caused by high energy particle strikes are becoming an increasingly important
problem in microprocessor design. With increasing transistor density and die sizes, soft
errors are expected to be a larger problem in the near future. Recovering from these
unexpected faults may be possible by reexecuting some part of the program only if the error
can be detected. Therefore it is important to come up with new techniques to detect soft
errors and increase the number of errors that are detected. Modern microprocessors employ
out-of-order execution and dynamic scheduling logic. Comparator circuits, which are used to
keep track of data dependencies, are usually idle. In this paper, we propose various schemes
to exploit on-chip comparators to detect transient faults. Our results show that around 50%
of the errors on the wakeup logic can be detected with minimal hardware overhead by using
the proposed techniques.
- A. Roth. "Physical Register Reference Counting." Computer Architecture Letters, vol. 6,
Oct. 2007.
Abstract:
Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and
NoSQ (No Store Queue) rely on reference counting to manage physical registers. However, the
register reference counting mechanism itself has received surprisingly little attention.
This paper fills this gap by describing potential register reference counting schemes for
NoSQ, CPR, and a hypothetical NoSQ/CPR hybrid. Although previously described in terms of
binary counters, we find that reference counts are actually more naturally represented as
matrices. Binary representations can be used as an optimization in specific situations.
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* SMART'08 Call for Papers: 2nd Workshop on Statistical and Machine learning approaches
to ARchitecture and compilaTion
********************************************************************************
CALL FOR PAPERS
2nd Workshop on
Statistical and Machine learning approaches
to ARchitecture and compilaTion
(SMART'08)
http://www.hipeac.net/smart-workshop.html
January 27, 2008, Goteborg, Sweden
(co-located with HiPEAC 2008 Conference)
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The rapid rate of architectural change has placed enormous pressure on
compiler writers to keep pace with microprocessor evolution. This
problem is compounded by the current trend to have multi-cores and
multi-threading which makes such systems increasingly difficult to
target. Also, current methods of designing computer systems will no
longer be feasible in 10-15 years time; what is needed are new
innovative approaches to architecture design that scale both with
advances in underlying technology and with future application domains.
In recent years, several papers have been published showing great
potential in constructing compilers and architectures using approaches
such as machine learning and search.
The purpose of this workshop is to promote new ideas and to present
recent developments in compiler and architecture design using machine
learning, statistical approaches, and search in order to enhance their
performance, scalability, and adaptability.
Topics of interest include (but are not limited to):
Machine Learning, Statistical Approaches, or Search applied to
* Feedback-Directed Compilation
* Auto-tuning Programs + Language Extensions
* Library Generators
* Iterative Compilation
* Dynamic Compilation/Adaptive Execution
* Parallel Compiler Optimizations
* Low-power Optimizations
* Simulation
* Performance Models
* Adaptive Processor and System Architecture
* Design Space Exploration
* Other Topics relevant to Intelligent and Adaptive Compilers/Architectures
**** Paper Submission Guidelines ****
Paper length - maximum 15 pages.
Papers must be submitted in the PDF (preferably) or postscript
formats. Email your submissions to mob@xxxxxxxxxxxx or use
the workshop submission website.
Proceedings: An informal collection of the papers to be presented will
be distributed at the workshop. Questions regarding the workshop
proceedings should be forwarded to mob@xxxxxxxxxxxx .
All accepted papers will appear on the workshop website.
Journal publication information:
The best papers submitted will be considered for publication
in the journal Transactions on HiPEAC, Springer-Verlag
**** Important Dates ****
Deadline for submission: November 16, 2007
Decision notification: December 16, 2007
Workshop: January 27, 2008
Organizer
Michael O'Boyle, University of Edinburgh UK
Program Committee
Francois Bodin, IRISA, France
Calin Cascaval, IBM T.J. Watson Research Center, USA
John Cavazos, University of Delaware, USA
Lieven Eeckhout, Ghent University, Belgium
Ari Freund, IBM Haifa Research Lab, Israel
Grigori Fursin, INRIA Futurs, France
Michael O'Boyle, University of Edinburgh, UK
David Padua, University of Illinois at Urbana-Champaign, USA
Devika Subramanian, Rice University, USA
Olivier Temam, INRIA Futurs, France
Matthew J. Thazhuthaveetil, Indian Institute of Science, India
Richard Vuduc, Georgia Institute of Technology, USA
David Whalley, Florida State University, USA
Chris Williams, University of Edinburgh, UK
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