This is the 1st May 2007 Digest of SIGARCH Messages (sigarch-may07a):
* PPoPP 2008 Call for Papers: 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
http://research.ihost.com/ppopp08/cfp.html (Papers)
http://research.ihost.com/ppopp08/cfwt.html (Workshops and Tutorials)
Submitted by Calin Cascaval <cascaval@xxxxxxxxxx>
* New papers published online by Computer Architecture Letters
http://www.comp-arch-letters.org
Submitted by Kevin Skadron <skadron@xxxxxxxxxxxxxxx>
* SBAC-PAD 2007 Call For Papers: 19th International Symposium on Computer Architecture and High Performance Computing
http://www.sbc.org.br/sbac/2007/
Submitted by Jean-Luc Gaudiot <gaudiot@xxxxxxx>
* The Phoenix System for Map Reduce Programming
http://csl.stanford.edu/~christos/sw/phoenix/
Submitted by Christos Kozyrakis <christos@xxxxxxxxxxxxxxx>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@xxxxxxx
* Archive: http://lists.cs.wisc.edu/archive/sigarch-members/
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@xxxxxxx with message body: unsubscribe SIGARCH-MEMBERS
-----------------------------------------------------------------
Doug Burger Office: 3.432 ACES
Associate Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-232-7460
The University of Texas at Austin Fax: 512-232-1413
1 University Station, #C0500 E-mail: dburger@xxxxxxxxxxxxx
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
----------------------------------------------------------------------
----------------------------------------------------------------------
* PPoPP 2008 Call for Papers: 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
PPoPP 2008 (http://www.ppopp.org)
Call for Papers
http://research.ihost.com/ppopp08/cfp.html
Call for Workshops and Tutorials
http://research.ihost.com/ppopp08/cfwt.html
13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
PPoPP 2008
February 20-23, 2008, Salt Lake City, Utah
http://www.ppopp.org
(Co-located with HPCA-14)
Call for Papers
PPoPP is a forum for leading work on all aspects of parallel programming,
including foundational results, techniques, tools, and practical
experience. In the context of the symposium, "parallel programming" is
construed to encompass work on concurrent, multithreaded, multicore,
multiprocessor, and tightly-clustered systems, but typically not wide-area
distribution. Given the rise of multicore processors, PPoPP is particularly
interested in work that seeks to transition parallel programming into the
computing mainstream.
Specific topics of interest include (but are not limited to):
* Parallel programming theory and models
* Formal analysis and verification
* Middleware for parallel systems
* Parallel programming languages
* Compilers and runtime systems
* Automatic parallelization
* Parallel libraries or application frameworks
* Performance analysis, debugging, and optimization
* Development, analysis, or management tools
* Parallel algorithms
* Parallel applications
* Concurrent data structures
* Synchronization and concurrency control
* Software engineering for parallel programs
* Fault tolerance for parallel systems
* Software issues for multicore or multithreaded processors
Papers should report on original research relevant to parallel programming,
and should contain enough background material to make them accessible to the
entire parallel programming research community. Papers describing experiences
should indicate how they illustrate general principles; papers about parallel
programming foundations should indicate how they relate to practice. Poster
submissions should meet similar criteria for originality and relevance, but
may present emerging ideas or results that are not yet sufficiently developed
for a full paper.
IMPORTANT DATES:
Abstract Submission: August 13, 2007 (5pm Eastern Daylight Time)
Full Paper Submission: August 20, 2007 (5pm Eastern Daylight Time)
Poster Submission: August 20, 2007 (5pm Eastern Daylight Time;
no separate abstract required)
Rebuttal Period: October 3-5, 2007
Notification of Acceptance: October 19, 2007
Workshop Submission: November 30, 2007
INFORMATION FOR AUTHORS:
All submissions must be made electronically through the conference web
site. Abstracts must include contact information, the full list of authors
and their affiliations, and a description (100-400 words) of the anticipated
content of the paper.
Full paper submissions must be in PDF format, viewable by Adobe Acrobat
Reader version 5.0 or higher, and formatted for US letter-size paper. They
must not exceed 10 pages (all inclusive) in standard ACM two-column
conference format (preprint mode, with page numbers). Over-length submissions
will be summarily discarded by the Program Chair.
Submissions will be judged on relevance, originality, significance, clarity,
and correctness.
Poster submissions must conform to the same format restrictions, but may not
exceed 2 pages in length. Paper submissions that are not accepted for regular
presentations will automatically be considered for posters; authors who do
not want their paper considered for the poster session should indicate this
in their abstract submission. Two-page summaries of posters will be included
in the conference proceedings.
The proceedings will be published by ACM Press. Authors of accepted papers
and posters will be required to sign the ACM copyright form. Instructions for
preparing papers for the proceedings will be emailed to authors of accepted
papers.
GENERAL CHAIR: Siddhartha Chatterjee, IBM Research
PROGRAM CHAIR: Michael L. Scott, Univ. of Rochester
PROGRAM COMMITTEE
Cristiana Amza, University of Toronto
Emery Berger, University of Massachussets
Greg Bronevetsky, Lawrence Livermore National Laboratory
Tim Harris, Microsoft
Liviu Iftode, Rutgers University
Vijay Karamcheti, New York University
Milo Martin, University of Pennsylvania
John Mellor-Crummey, Rice University
Maged Michael, IBM Research
Bratin Saha, Intel
Michael Scott, University of Rochester
Marc Shapiro, INRIA
Lauren Smith, U.S. Department of Defense
Nir Shavit, Sun, Tel Aviv University
Philippas Tsigas, Chalmers University
Jeff Vetter, Oak Ridge National Laboratory
Antonia Zhai, University of Minnessota
Yutao Zhong, George Mason University
--- Call for Workshops and Tutorials
The ACM SIGPLAN Symposium on Principles and Practice of Parallel
Programming (PPoPP) 2008 is seeking proposals for workshops and
tutorials to accompany the conference. Workshops and tutorials will be
held on Saturday, February 23, 2008 and may be a half day or a full
day in length.
The deadline for workshop and tutorial proposals is October 10,
2007. Please send all proposals to the workshops/tutorials chair,
David Lowenthal, at dkl@xxxxxxxxxxx Please start the subject line with
PPoPP 2008:.
We encourage members of the community to consider submitting proposals
for workshops that bring together researchers and practitioners
working on research topics of significant current interest, as well as
workshops that bring together researchers and practitioners working in
particular areas.
Workshop proposals should include:
* The workshop title
* The organizers and their affiliations
* A description of the workshop and/or a proposed call for participation
or papers
* The proposed length of the workshop (half day or full day; if half day,
planned length in hours)
* If the workshop was previously held, the number of attendees at the last
workshop and the number of presentations or papers given at the workshop.
Tutorial proposals should include:
* The tutorial title
* Organizers, presenters, and their affiliations
* A description of the tutorial
* The proposed length of the tutorial (half day or full day; if half day,
planned length in hours)
* If the tutorial has been given previously, the location, date, and
number of attendees at the last tutorial.
----------------------------------------------------------------------
----------------------------------------------------------------------
* New papers published online by Computer Architecture Letters
Computer Architecture Letters announces our four most recent papers. We continue to seek new submissions and remain committed to fast and accurate review. Our mean time to decision in 2007 has been 24 days, and our acceptance rate is currently about 23%. For more information on submission, please see http://www.comp-arch-letters.org
- Sreekumar Kodakara, Jinpyo Kim, David Lilja, Douglas Hawkins, Wei-Chung Hsu, Pen-Chung Yew, "CIM: A Reliable Metric for Evaluating Program Phase Classifications," IEEE Computer Architecture Letters, vol. 6, no. 1, Apr. 2007.
- Miquel Moreto Planas, Francisco Cazorla, Alex Ramirez, Mateo Valero, "Explaining Dynamic Cache Partitioning Speed Ups," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007.
- Natalie Enright Jerger, Mikko Lipasti, Li-Shiuan Peh, "Circuit-Switched Coherence," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007.
- William R. Dieter, Akil Kaveti, Henry G. Dietz, "Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007.
Abstracts
---------
- Sreekumar Kodakara, Jinpyo Kim, David Lilja, Douglas Hawkins, Wei-Chung Hsu, Pen-Chung Yew, "CIM: A Reliable Metric for Evaluating Program Phase Classifications," IEEE Computer Architecture Letters, vol. 6, no. 1, Apr. 2007.
Abstract:
We propose the use of the Confidence Interval of estimated Mean (CIM), a metric based on statistical sampling theory, to evaluate the quality of a given phase classification and for comparing different phase classification schemes. Previous research on phase classification used the Weighted Average of Coefficient of Variation (CoVwa) to estimate phase classification quality. We found that the phase quality indicated by CoVwa could be inconsistent across different phase classifications. We explain the reasons behind this inconsistency and demonstrate the inconsistency using data from several SPEC CPU2000 benchmark programs. We show that the Confidence Interval of estimated Mean (CIM) correctly estimates the quality of phase classification with a meaningful statistical interpretation.
- Miquel Moreto Planas, Francisco Cazorla, Alex Ramirez, Mateo Valero, "Explaining Dynamic Cache Partitioning Speed Ups," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007.
Abstract:
Cache Partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups.
- Natalie Enright Jerger, Mikko Lipasti, Li-Shiuan Peh, "Circuit-Switched Coherence," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007.
Abstract:
Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, communication latency approaches pure interconnect delay. However, if circuits are not frequently reused, the long set up time and poorer interconnect utilization can hurt overall performance. To combat this problem, we propose a hybrid router design which intermingles packet-switched flits with circuit-switched flits. Additionally, we co-design a prediction-based coherence protocol that leverages the existence of circuits to optimize pair-wise sharing between cores. The protocol allows pair-wise sharers to communicate directly with each other via circuits and drives up circuit reuse. Circuit-switched coherence provides overall system performance improvements of up to 17% with an average improvement of 10% and reduces network latency by up to 30%.
- William R. Dieter, Akil Kaveti, Henry G. Dietz, "Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy," IEEE Computer Architecture Letters, vol. 6, no. 1, Mar. 2007.
Abstract:
Some processors designed for consumer applications, such as Graphics Processing Units (GPUs) and the CELL processor, promise outstanding floating-point performance for scientific applications at commodity prices. However, IEEE single precision is the most precise floating-point data type these processors directly support in hardware. Pairs of native floating point numbers can be used to represent a base result and a residual term to increase accuracy, but the resulting order of magnitude slowdown dramatically reduces the price/performance advantage of these systems.
By adding a few simple microarchitectural features, acceptable accuracy can be obtained with relatively little performance penalty. To reduce the cost of native-pair arithmetic, a residual register is used to hold information that would normally have been discarded after each floating-point computation. The residual register dramatically simplifies the code, providing both lower latency and better instruction-level parallelism.
----------------------------------------------------------------------
----------------------------------------------------------------------
* SBAC-PAD 2007 Call For Papers: 19th International Symposium on Computer Architecture
and High Performance Computing
===========================================================
CALL FOR PAPERS
SBAC-PAD 2007
19th International Symposium on Computer Architecture
and High Performance Computing
Gramado, Brazil October 24-27, 2007
http://www.sbc.org.br/sbac/2007/
Sponsors: Brazilian Computer Society
IEEE Computer Society (pending)
===========================================================
SBAC-PAD is an annual international conference series, the
first of which was held 20 years ago, in 1987. Each
conference has traditionally presented new developments and
high performance applications, as well as the latest trends
in computer architecture and parallel and distributed
technologies. This year, the symposium returns to Gramado,
Rio Grande do Sul, Brazil. The conference will be held at
the Hotel "Serra Azul," located in the heart of downtown
Gramado and within walking distance of the main tourist
attractions.
SBAC_PAD 2007 will be sponsored by the Brazilian Computer
Society, the IEEE Computer Society (approval pending)
through the Technical Committees on Computer Architecture
(TCCA) and Scalable Computing (TCSC), and IFIP. Authors are
invited to submit manuscripts that present original
unpublished research in all areas of computer architecture
and high performance computing. Work focusing on
applications or emerging technologies is especially
welcome. Topics of interest include, but are not limited
to:
- Application-specific Architectures
- Benchmarking, Performance Measurements and Analysis
- Cache and Memory Architectures
- Embedded Systems
- Fault-Tolerant Architectures and Systems
- Grid, Cluster, and Peer-to-Peer Computing
- High Performance Applications and Parallel and
Distributed Algorithms
- Interconnection Networks, Routing, and Communication
- Languages, Compilers and Tools for Parallel and
Distributed Programming
- Load Balancing and Scheduling
- Microarchitecture
- Operating Systems and Virtualization
- Parallel and Distributed Architectures
- Pervasive and Heterogeneous Computing
- Real World Applications and Case Studies
- Reconfigurable Systems
SBAC-PAD invites manuscripts of original research, written
in English and not exceeding 8 pages in double column
following the IEEE Conference style, to be submitted in PDF
format. The proceeding will be published by the IEEE
Computer Society Press.
A blind submission and review process will be used,
therefore papers should be submitted without the authors'
names on the manuscript. Moreover, authors should take any
reasonable precautions to hide their identity. Citations to
the authors' own prior work can be included, but references
should be in the third person. Please check the SBAC-PAD
2007 web site for further paper submission and format
information: http://www.sbc.org.br/sbac/2007/
The authors of selected papers will also be invited to
submitted extended versions of their work for possible
publication in a special issue of the International Journal
of Parallel Programming.
Important Dates
---------------
- Paper Submission deadline May 28, 2007
- Author Notification July 09, 2007
- Conference October 24-27, 2007
General Chair
-------------
Philippe O. Alexandre Navaux (UFRGS, Brazil)
Program Co-chairs
-----------------
Jean-Luc Gaudiot (UCI, USA)
Vinod Rebello (UFF, Brazil)
Steering Committee
------------------
Alberto F. de Souza (UFES, Brazil)
Cláudio L. Amorim (UFRJ, Brazil)
Jairo Panetta (INPE, Brazil)
Jean-Luc Gaudiot (UCI, USA)
Líria M. Sato (USP, Brazil)
Philippe O. Alexandre Navaux (UFRGS, Brazil)
Rajkumar Buyya (UMelb, Australia)
Siang W. Song (USP, Brazil)
Organizing Committee
--------------------
Adenauer Yamin (UCPEL, Brazil)
Denise Grüne Ewald (CESUP, UFRGS, Brazil)
Lourdes Tassinari (UFRGS, Brazil)
Lucas Schnorr (UFRGS, Brazil)
Nicolas Maillard (UFRGS, Brazil)
Philippe Navaux (UFRGS, Brazil)
Tatiana Santos (UNISC, Brazil)
Vinod Rebello (UFF, Brazil)
Wagner Meira (UFMG, Brazil)
Program Committee
-----------------
Alba Melo (UnB, Brazil)
Alberto De Souza (UFES, Brazil)
Alex Nicolau (University of California, Irvine, USA)
Alfredo Goldman (USP, Brazil)
Alvaro Coutinho (UFRJ, Brazil)
Bertil Folliot (University Pierre et Marie Curie, Paris VI, France)
Bruno Schulze (LNCC, Brazil)
Celso Mendes (University of Illinois, USA)
Cesar De Rose (PUCRS, Brazil)
Christophe Cerin (Universit Paris 13, France)
Claudio Amorim (UFRJ, Brazil)
Claudio Geyer (UFRGS, Brazil)
Cristina Boeres (UFF, Brazil)
D. Janakiram (Indian Institute of Technology, Madras India)
David Kaeli (Northeastern University, USA)
Denis Trystram (IMAG, France)
Edil Fernandes (UFRJ, Brazil)
Edson Cáceres (UFMS, Brazil)
Eduardo Bergamini (INPE/CPTEC, Brazil)
Felipe França (UFRJ, Brazil)
Francisco Brasileiro (UFCG, Brazil)
Frank Dehne (Carleton University, USA)
Gabriel P. Silva (UFRJ, Brazil)
Geoffrey Fox (Indiana University, USA)
Jack Dongarra (University of Tennessee, USA)
Jairo Panetta (INPE/CPTEC, Brazil)
Jean-Luc Gaudiot (University of California, Irvine, USA)
José Fortes (University of Florida, USA)
Jose Moreira (IBM, USA)
José Saito (UFSC, Brazil)
Kuan-Ching Li (Providence University, USA)
Lalit Patnaik (Indian Institute of Science, India)
Laurence Yang (St Francis Xavier University, Canada)
Liria Sato (USP, Brazil)
Lucia Catabriga (UFES, Brazil)
Lucia Drummond (UFF, Brazil)
Luiz Barroso (Google, USA)
Luiz DeRose (Cray Inc., USA)
Luiza Mourelle (UERJ, Brazil)
Maria Clicia de Castro (UERJ, Brazil)
Mario Nemirovsky (ConSentry Networks, USA)
Mateo Valero (Technical University of Catalonia, Spain)
Nader Bagherzadeh (University of California, Irvine, USA)
Noemi Rodrigues (PUC-Rio, Brazil)
Orlando Loques (UFF, Brazil)
Osni Marques (Lawrence Berkeley National Laboratory, USA)
Peter Rounce (University College London, UK)
Philippe Navaux (UFRGS, Brazil)
Priscila M V Lima (UFRJ, Brazil)
Rafael Lins (UFPE, Brazil)
Rajkumar Buyya (University of Melbourne, Australia)
Renato Silva (LNCC, Brazil)
Ricardo Bianchini (Rutgers University, USA)
Ricardo Corrêa (UFC, Brazil)
Ron Perrott (Queen's University Belfast, UK)
Ronaldo Goncalves (Universidade Estadual de Maringá, Brazil)
Sérgio Kofuji (USP, Brazil)
Siang Song (USP, Brazil)
Srikumar Venugopal (University of Melbourne, Australia)
Valmir Barbosa (UFRJ, Brazil)
Viktor Prasanna (University of Southern California, USA)
Vinod Rebello (UFF, Brazil)
Wagner Meira, Jr. (UFMG, Brazil)
Yale Patt (University of Texas at Austin, USA)
----------------------------------------------------------------------
----------------------------------------------------------------------
* The Phoenix System for Map Reduce Programming
**One line summary**
The Phoenix System for Map Reduce Programming
(http://csl.stanford.edu/~christos/sw/phoenix/)
**Longer Summary:**
The Phoenix System for Map Reduce Programming
Phoenix is shared-memory implementation of Google's MapReduce
<http://labs.google.com/papers/mapreduce.html> model for data-intensive processing tasks.
Phoenix can be used to program multi-core schips as well as shared-memory multiprocessors
(SMPs and ccNUMAs). The paper <http://csl.stanford.edu/%7Echristos/publications/2007.cmp_
mapreduce.hpca.pdf> on Phoenix won the best paper award in the HPCA'07
<http://www.hpcaconf.org/hpca13> conference. To download Phoenix, please go to:
http://csl.stanford.edu/~christos/sw/phoenix/
|
![[Computer Systems Lab]](https://www-auth.cs.wisc.edu/pics/csl_logo.gif){kind=logo}