[Gems-users] profiling L1 and stat inconsistency

["Mladen Nikitovic" <mladen@xxxxxxxxxxx>]

Hi,

Two questions:

Previously, I recieved a tip that I could profile L1 cache accesses/misses
on a per processor basis by adding profiling code to the Sequencer.

I found that one could extend the integer counters (in Profiler functions
addL1DStatSample and addL1IStatSample) into vectors and distinguish the L1
accesses there. To distinguish total number of (instruction and data) L1
accesses on a per processor basis, I used the same vector-solution in the
SimicsDriver function recordTransactionStats. Does this approach sound
reasonable to you? I'm afraid that I could miss some stats, which leads me
to my next question...

I discovered a inconsistency in my stats that I could not understand. In the
Simics Driver Transaction Stats I found that the sum of Insn and Data
(17,285,301) does not match the number of Fast path accesses in the Simics
Driver Transaction Result Stats. Is it because there are requests that does
not go through the caches or is it due to some other reason? Any ideas?

My Simics Driver Stats looks like this: 

Simics Driver Transaction Stats
----------------------------------
Insn requests: 13869063 [ 3262320 3024289 3460288 4122166 ]
Data requests: 3416238 [ 798931 748882 861595 1006830 ]
Memory mapped IO register accesses: 0
Device initiated accesses: 0
Other initiated accesses: 0
Atomic load accesses: 174
Exceptions: 295
Non stallable accesses: 651
Prefetches: 0
Cache Flush: 0

Requests of asi 0x4: 44120
Requests of asi 0x10: 33
Requests of asi 0x11: 19
Requests of asi 0x14: 4062
Requests of asi 0x24: 26
Requests of asi 0x34: 148
Requests of asi 0x80: 17236893

Simics Driver Transaction Results Stats
------------------------------------------
Fast path: 17279244
Request missed: 5406
Sequencer not ready: 0
Duplicate instruction fetches: 2427
Hit return: 2746
Atomic last accesses: 231


Best Regards,
Mladen