Dave Z. wrote:
Hello All,
I'd like to modify the way the L1/L2 cache requests
are handled in MOESI_SMP_hammer. For example, I'd like
to add new functionalities on certain transitions. So,
I'm wondering if modifying MOESI_SMP_hammer-cache.sm
(actions and transitions) will be enough. Or do I need
to define new objects and put them in ruby/system
(just like the DemoPrefetcher example in the slides)?
You don't need to add additional components, unless you want to add
them. It's certainly possible to change the controller behavior (in the
.sm file) without adding new components. But it might be convenient to
do so. The choice is up to you.
Also, if I add a new controller to the system rather
than modifying the original code, how will I introduce
the new controller to the system? Will
MOESI_SMP_hammer-NEWCONTROLLER.sm be enough?
To add a new controller, add it to the MOESI_SMP_hammer.slicc file.
I'd like to get the big picture of how the memory
model works. For example, when data is brought from
the memory, what components are involved. Only the
cache controller? How about the Sequencer? What is the
responsibility of the Sequencer? When is
MOESI_SMP_hammer-dir.sm used?
I'm not totally confident in this answer, but I believe that the data is
actually read from memory by Simics. When Ruby (the timing model) tells
Simics that the load is complete, the value that is stored in the
physical memory object is retrieved by the Simics processor model. In
other words, data doesn't get moved around by Ruby.
The directory controller is used when it receives a message from a
cache. Ruby is event-driven -- the cache controller sends a message to
the directory in response to a cache miss; when that message arrives at
the directory, it triggers an event that is handled by the controller.
Finally, is it possible to make data transfers between
processors? Is there something like
processor0.L2cacheMemory[address] =
processor1.L2cacheMemory[address]? How can I obtain
the machine id's of other processors in the system?
First, there's no data kept in the caches. Second, unless you wanted to
somehow circumvent the timing model and do something like this
instantaneously, this is not what you want to do. If you want to model
a cache line being transferred between caches, you should create
messages that are sent from one cache to the other, then allocate a
cache line in the receiving cache, etc., etc.
...Greg Byrd
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